73S8010R
Low Cost Smart Card Interface
DATA SHEET
I2C-bus Read from Status Register:
I2C-bus Read Command from the Status Register follows the format shown below. After the START condition, a
slave address is sent by the master. This address is seven bits long followed by an eighth bit which is an opcode
bit (R/W) – a ‘one’ indicates the master will read data from the status register. After the R/W bit, the ’zero’ ACK bit
is sent to the master by the device. The device now starts sending the 8-bit status register data to the control
register during the DATA bits. After the DATA bits, the ‘one’ ACK bit is sent to the device by the master. The
master should send the STOP condition after receiving the ACK bit.
SDA
MSB
LSB
MSB
LSB
SCL
9
1-7
8
9
1-8
START
STOP
ACK bit
ADDRESS bits
R/W bit
DATA bits
ACK bit
condition
condition
Figure 3 - I2C Bus Read Protocol
I2C-bus timing definition:
S D A
T b u f
S C L
T lo w
T h i
T h d s ta
T s u d a t
T h d d a t
T s u s to
Figure 4 - I2C Bus Timing Definitions
Symbol Parameter
Min.
Typ. Max. Unit
Fsclk
Clock frequency
400
kHz
µs
µs
µs
ns
ns
µs
Tlow
Clock low
1.3
0.6
0.6
100
5
Thi
Clock high
Thdsta
Tsudat
Thddat
Tsusto
Hold time START condition
Data set up time
Data hold time
900
Set up time STOP condition
Bus free time between a STOP
and START condition
0.6
Tbuf
1.3
µs
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© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
