73S8010R
Low Cost Smart Card Interface
DATA SHEET
SYSTEM CONTROLLER INTERFACE (I2C BUS)
A fast-mode 400kHz I2C bus slave interface is used for controlling the device and reading the status of the device
via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0, SAD1, and SAD2. This
allows up to 8 devices to be connected in parallel.
Device Address Selections
I2C Address
SAD2 SAD1 SAD0
(7 bits)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
Note: bit 0 of the I2C address is the R/W bit. Refer to figures 2 and 3 for usage.
CONTROL register
Power On Reset = 00h
Name
Bit Description
When set, initiates an activation and a cold reset procedure; when reset, initiates
Start/Stop
Warm reset
5Vand 3V
0
1
2
a deactivation sequence
When set, initiates a warm reset procedure; automatically reset by hardware
when the card starts answering or when the card is declared mute
When set, VCC = 3v; when reset, VCC = 5v. When de-activating (setting bit 0 = 0)
and operating with 3V (bit 2 =1), do not simultaneously set bit 2 =0.
When set, the card clock is stopped. Bit 4 determines the card clock stop level
When set, card clock stops high; when reset card clock stops low
Clock Stop
Clock Stop Level
Clksel1
3
4
5
6
Bits 5 and 6 determine the clock rate to the. See card clock rate selection table
for more details.
Clksel2
I/O enable bit. When set, I/O is transferred on I/OUC; when reset I/O to I/OUC is
high impedance.
I/O enable
7
Card clock rate selection table
Bit Clksel2 Bit Clksel1 Card Clock
0
0
1
1
0
1
0
1
Clkin/8
Clkin/4
Clkin/2
Clkin (Xtalin)
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© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
