73S8010R
Low Cost Smart Card Interface
DATA SHEET
PIN DESCRIPTION
CARD INTERFACE
PIN
PIN
NAME
DESCRIPTION
(SO)
(QFN)
8
I/O
11
13
12
16
Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC.
AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
Card reset: provides reset (RST) signal to card.
AUX1
AUX2
RST
11
10
14
Card clock: provides clock (CLK) signal to card. The rate of this clock is determined by crystal
oscillator frequency and CLKSEL bits in the control register.
CLK
15
10
17
14
13
7
PRES
VCC
GND
Card Presence switch: active high indicates card is present. Includes a pull-down resistor.
Card power supply – logically controlled by sequencer, output of LDO regulator. Requires an
external filter capacitor to the card GND.
15
12
Card ground.
MISCELLANEOUS INPUTS AND OUTPUTS
PIN
PIN
NAME
DESCRIPTION
(SO)
(QFN)
XTALIN
XTALOUT
24
23
Crystal oscillator input: can either be connected to crystal or driven as a source for the card clock.
Crystal oscillator output: connected to crystal. Left open if XTALIN is being used as external
clock input.
25
24
V
DD threshold adjustment input: this pin can be used to overwrite higher VDDF value (that controls
VDDF_ADJ
NC
18
17
deactivation of the card). Must be left open if unused.
4, 5, 6,
9, 16,
7, 8, 9
Non-connected pin.
25, 32
POWER SUPPLY AND GROUND
PIN
PIN
NAME
DESCRIPTION
(SO)
(QFN)
VDD
VPC
GND
GND
GND
21
6
20
3
System controller interface supply voltage and supply voltage for internal circuitry.
LDO regulator power supply source.
LDO regulator ground.
Smart Card I/O Ground.
Digital ground.
4
1
14
5, 22
12
2,21
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© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
