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73S8010C-IMR/F 参数 Datasheet PDF下载

73S8010C-IMR/F图片预览
型号: 73S8010C-IMR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 智能卡接口 [Smart Card Interface]
分类和应用: 模拟IC信号电路
文件页数/大小: 27 页 / 334 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73S8010C Data Sheet  
DS_8010C_024  
Figures  
Figure 1: 73S8010C Block Diagram .............................................................................................................2  
Figure 2: I2C Bus Write Protocol ...................................................................................................................8  
Figure 3: I2C Bus Read Protocol...................................................................................................................9  
Figure 4: I2C Bus Timing Diagram ................................................................................................................9  
Figure 5: Power Down Mode Operation......................................................................................................12  
Figure 6: Activation Sequence....................................................................................................................12  
Figure 7: Deactivation Sequence................................................................................................................13  
Figure 8: FAULT Functions, INT operation.................................................................................................13  
Figure 9: Warm Reset operation.................................................................................................................14  
Figure 10: I/O Timing ..................................................................................................................................14  
Figure 11: 73S8010C – Typical Application Schematic..............................................................................15  
Figure 12: DC – DC Converter Efficiency (VCC = 5 V) ................................................................................18  
Figure 13: DC – DC Converter Efficiency (VCC = 3 V) ................................................................................18  
Figure 14: 32-pin QFN Package Drawing...................................................................................................22  
Figure 15: 28-pin SO Package Drawing .....................................................................................................23  
Tables  
Table 1: Device Address Selections .............................................................................................................7  
Table 2: Host Control Register......................................................................................................................7  
Table 3: Host Status Register .......................................................................................................................8  
Table 4: Choice of Vcc Capacitor ...............................................................................................................10  
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