73S8009R Data Sheet
DS_8009R_056
Figures
Figure 1: 73S8009R Block Diagram.........................................................................................................2
Figure 2: 73S8009R 20-Pin QFN Pinout ..................................................................................................5
Figure 3: 73S8009R 28-Pin SO Pinout.....................................................................................................5
Figure 4: Typical 73S8009R Application Schematic ...............................................................................13
Figure 5: Activation Sequence...............................................................................................................15
Figure 6: Deactivation Sequence...........................................................................................................16
Figure 7: OFF Activity Outside and Inside a Card Session .....................................................................17
Figure 8: Power-down Operation ...........................................................................................................17
Figure 9: CS Timing Definitions..............................................................................................................18
Figure 10: I/O and I/OUC State Diagram................................................................................................19
Figure 11: I/O to I/OUC Delay Timing Diagram.......................................................................................19
Figure 12: 20-pin QFN Package Dimensions .........................................................................................20
Figure 13: 28-Pin SO Package Dimensions ...........................................................................................21
Tables
Table 1: 73S8009R Pin Definitions ..........................................................................................................6
Table 2: Absolute Maximum Device Ratings ............................................................................................8
Table 3: Recommended Operating Conditions.........................................................................................8
Table 4: DC Smart Card Interface Requirements .....................................................................................9
Table 5: Digital Signals Characteristics ..................................................................................................11
Table 6: DC Characteristics ...................................................................................................................11
Table 7: Voltage / Temperature Fault Detection Circuits.........................................................................12
Table 8: Choice of VCC Pin Capacitor ...................................................................................................15
Table 9: Order Numbers and Packaging Marks......................................................................................22
4
Rev. 1.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
