DS_8009CN_026
73S8009CN Data Sheet
Equivalent
Circuit
Pin
Name
Pin
Number
Type
Description
DM
23
IO
Figure 14
USB D- connection to / from USB controller.
When SC/USB is set low, this pin is electrically
connected to the AUX1 pin, otherwise it is isolated.
CMDVCC%
CMDVCC#
4
5
I
I
Figure 19
Logic low on one or both of these pins will cause the
LDO regulator to ramp the Vcc supply to the smart
card and smart card interface to the value described
in the following table:
CMDVCC%
CMDVCC#
Vcc Output Voltage
0
0
1
1
0
1
0
1
1.8V
5.0V
3.0V
Vcc Off
Note: See Card Power Supply and Voltage
Supervision for more details.
6
8
I
Figure 19
Figure 12
RSTIN
RDY
Reset Input: This signal is the reset command to the
card.
O
Signal to controller indicating the 73S8009CN is
ready because VCC is above the required value after
CMDVCC% and/or CMDVCC# is asserted low. A
20kΩ pull-up resistor to VDD is provided internally.
Pull-up is disabled in Power down state and CS=0
modes.
ON/OFF
24
I
Figure 11
Power control pin. Connected to normally open
SPST switch to ground. Closing switch for duration
greater than de-bounce period will turn 73S8009CN
circuit “on”. If the 73S8009CN is “on,” closing the
switch will turn 73S8009CN to “off” state after the
de-bounce period and OFF_REQ/OFF_ACK
handshake. Can be controlled by a host processor
digital output.
OFF_REQ
OFF_ACK
11
13
O
I
Figure 19
Figure 19
Digital output. Request to the host system controller
to turn the 73S8009CN off. If ON_OFF switch is
closed (to ground) for de-bounce duration and circuit
is “on,” OFF_REQ will go high (request to turn OFF).
Connected to OFF_ACK via 100kΩinternal resistor.
Setting OFF_ACK high will power “off” all analog
functions and disconnect the 73S8009CN from VPC.
The pin has an internal 100kΩ resistor connection to
OFF_REQ so that when not connected or no host
interaction is required, the Acknowledge will be true
and the circuit will turn “off” after the deactivation
sequence is completed.
Miscellaneous
CLKIN
7
I
Figure 19
Clock signal source for the card clock.
TEST1
10
30
–
–
–
–
Factory test pin. This pin must be tied to GND.
Factory test pin. This pin must be tied to GND.
TEST2
Rev. 1.4
7
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
