73S1217F Data Sheet
DS_1217F_002
Figures
Figure 1: IC Functional Block Diagram......................................................................................................... 7
Figure 2: Memory Map................................................................................................................................ 15
Figure 3: Clock Generation and Control Circuits ........................................................................................ 23
Figure 4: Oscillator Circuit........................................................................................................................... 25
Figure 5: Detailed Power Management Logic Block Diagram.................................................................... 26
Figure 6: Power-Down Control.................................................................................................................... 29
Figure 7: Detail of Power-Down Interrupt Logic.......................................................................................... 30
Figure 8: Power-Down Sequencing............................................................................................................ 30
Figure 9: External Interrupt Configuration................................................................................................... 35
Figure 10: Real Time Clock Block Diagram................................................................................................ 54
Figure 11: I2C Write Mode Operation.......................................................................................................... 61
Figure 12: I2C Read Operation ................................................................................................................... 62
Figure 13: Simplified Keypad Block Diagram ............................................................................................. 67
Figure 14: Keypad Interface Flow Chart..................................................................................................... 69
Figure 15: USB Block Diagram................................................................................................................... 75
Figure 16: Smart Card Interface Block Diagram......................................................................................... 78
Figure 17: Smart Card Interface Block Diagram......................................................................................... 79
Figure 18: Asynchronous Activation Sequence Timing.............................................................................. 81
Figure 19: Deactivation Sequence.............................................................................................................. 82
Figure 20: Smart Card CLK and ETU Generation ...................................................................................... 83
Figure 21: Guard, Block, Wait and ATR Time Definitions .......................................................................... 84
Figure 22: Synchronous Activation ............................................................................................................. 86
Figure 23: Example of Sync Mode Operation: Generating/Reading ATR Signals ..................................... 86
Figure 24: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode................................. 87
Figure 25: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode ................................. 87
Figure 26: Operation of 9-bit Mode in Sync Mode...................................................................................... 88
Figure 27: 73S1217F Typical Application Schematic (Handheld USB PINpad, with Combo USB-
Bus and Self-powered Configuration)..................................................................................... 114
Figure 28: 73S1217F Typical Application Schematic (USB Transparent Reader and USB Key
Configuration).......................................................................................................................... 115
Figure 29: 12 MHz Oscillator Circuit......................................................................................................... 126
Figure 30: 32KHz Oscillator Circuit........................................................................................................... 126
Figure 31: Digital I/O Circuit...................................................................................................................... 127
Figure 32: Digital Output Circuit................................................................................................................ 127
Figure 33: Digital I/O with Pull Up Circuit.................................................................................................. 128
Figure 34: Digital I/O with Pull Down Circuit............................................................................................. 128
Figure 35: Digital Input Circuit................................................................................................................... 129
Figure 36: OFF_REQ Interface Circuit ..................................................................................................... 129
Figure 37: Keypad Row Circuit ................................................................................................................. 130
Figure 38: Keypad Column Circuit............................................................................................................ 130
Figure 39: LED Circuit............................................................................................................................... 131
Figure 40: Test and Security Pin Circuit ................................................................................................... 131
Figure 41: Analog Input Circuit ................................................................................................................. 132
Figure 42: Smart Card Output Circuit ....................................................................................................... 132
Figure 43: Smart Card I/O Circuit ............................................................................................................. 133
Figure 44: PRES Input Circuit................................................................................................................... 133
Figure 45: USB Circuit ..............................................................................................................................134
Figure 46: ON_OFF Input Circuit.............................................................................................................. 134
Figure 47: 73S1217F Pinout..................................................................................................................... 135
Figure 48: 73S1217F 68 QFN Mechanical Drawing................................................................................. 136
4
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
