73S1215F Data Sheet
DS_1215F_003
Figures
Figure 1: IC Functional Block Diagram ......................................................................................................... 7
Figure 2: Memory Map................................................................................................................................ 15
Figure 3: Clock Generation and Control Circuits ........................................................................................ 24
Figure 4: Oscillator Circuit........................................................................................................................... 26
Figure 5: Power Down Control.................................................................................................................... 27
Figure 6: Detail of Power Down Interrupt Logic .......................................................................................... 28
Figure 7: Power Down Sequencing ............................................................................................................ 28
Figure 8: External Interrupt Configuration................................................................................................... 33
Figure 9: Real Time Clock Block Diagram.................................................................................................. 52
Figure 10: I2C Write Mode Operation.......................................................................................................... 59
Figure 11: I2C Read Operation.................................................................................................................... 60
Figure 12: Simplified Keypad Block Diagram.............................................................................................. 65
Figure 13: Keypad Interface Flow Chart .................................................................................................... 67
Figure 14: USB Block Diagram ................................................................................................................... 72
Figure 15: Smart Card Interface Block Diagram......................................................................................... 76
Figure 16: Smart Card Interface Block Diagram......................................................................................... 77
Figure 17: Asynchronous Activation Sequence Timing .............................................................................. 79
Figure 18: Deactivation Sequence.............................................................................................................. 80
Figure 19: Smart Card CLK and ETU Generation ...................................................................................... 81
Figure 20: Guard, Block, Wait and ATR Time Definitions........................................................................... 82
Figure 21: Synchronous Activation ............................................................................................................. 84
Figure 22: Example of Sync Mode Operation: Generating/Reading ATR Signals ..................................... 84
Figure 23: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode................................. 85
Figure 24: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode ................................. 85
Figure 25: Operation of 9-bit Mode in Sync Mode ...................................................................................... 86
Figure 26: 73S1215F Typical Application Schematic ............................................................................... 111
Figure 27: 12 MHz Oscillator Circuit ......................................................................................................... 120
Figure 28: 32kHz Oscillator Circuit ........................................................................................................... 120
Figure 29: Digital I/O Circuit...................................................................................................................... 121
Figure 30: Digital Output Circuit................................................................................................................ 121
Figure 31: Digital I/O with Pull Up Circuit.................................................................................................. 122
Figure 32: Digital I/O with Pull-Down Circuit............................................................................................. 122
Figure 33: Digital Input Circuit................................................................................................................... 123
Figure 34: Keypad Row Circuit ................................................................................................................. 123
Figure 35: Keypad Column Circuit............................................................................................................ 124
Figure 36: LED Circuit............................................................................................................................... 125
Figure 37: Test and Security Pin Circuit ................................................................................................... 125
Figure 38: Analog Input Circuit.................................................................................................................. 126
Figure 39: Smart Card Output Circuit ....................................................................................................... 126
Figure 40: Smart Card I/O Circuit.............................................................................................................. 127
Figure 41: PRES Input Circuit................................................................................................................... 127
Figure 42: PRES Input Circuit................................................................................................................... 128
Figure 43: USB Circuit ..............................................................................................................................128
Figure 44: 73S1215F 68 QFN Pinout ....................................................................................................... 129
Figure 45: 73S1215F 44 QFN Pinout ....................................................................................................... 130
Figure 46: 73S1215F 68 QFN Package Drawing ..................................................................................... 131
Figure 47: 73S1215F 44 QFN Package Drawing ..................................................................................... 132
4
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
