DS_1209F_004
73S1209F Data Sheet
Pin Name
Description
INT2
SIO
52
50
32
31
I
Figure 31 General purpose interrupt input.
IO
Figure 27 IO data signal for use with external Smart Card interface
circuit such as 73S8010.
SCLK
PRES
48
64
30
43
O
I
Figure 28 Clock signal for use with external Smart Card interface
circuit.
Figure 39 Smart Card presence. Active high. Note: the pin has a
very weak pull down resistor. In noisy environments, an
external pull down may be desired to insure against a
false card event.
PRESB
56
35
I
Figure 40 Smart Card presence. Active low. Note: the pin has a
very weak pull up resistor. In noisy environments, an
external pull up may be desired to insure against a false
card event.
CLK
RST
IO
57
59
63
62
61
60
36
38
42
41
40
O
O
Figure 37 Smart card clock signal.
Figure 37 Smart card Reset signal.
IO
IO
IO
Figure 38 Smart card Data IO signal.
Figure 38 Auxiliary Smart Card IO signal (C4).
Figure 38 Auxiliary Smart Card IO signal (C8).
AUX1
AUX2
VCC
39 PSO
Smart Card VCC supply voltage output. A 0.47μF
capacitor is required and should be located at the smart
card connector. The capacitor should be a ceramic type
with low ESR.
GND
VPC
58
55
37 GND
Smart Card Ground.
34
PSI
IO
Smart Card LDO regulator power supply source. A
10μF and a 0.1μF capacitor are required at the VPC
input. The 10μF capacitor should be a ceramic type
with low ESR.
TBUS(3:0)
0
1
2
3
53
49
47
43
Trace bus signals for ICE.
RXTX
ERST
ISBR
TCLK
45
40
68
41
28
25
IO
IO
IO
I
ICE control.
ICE control.
ICE control.
ICE control.
26
10
2
Figure 36 Analog input pin. This signal goes to a programmable
comparator and is used to sense the value of an
external voltage.
ANA_IN
SEC
15
67
54
AI
I
Figure 35 Input pin for use in programming security fuse. It should
be connected to ground when not in use.
TEST
33
DI
Figure 35
Test pin, should be connected to ground.
Rev. 1.2
9
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
