欢迎访问ic37.com |
会员登录 免费注册
发布采购

73S1121F-CGV/F 参数 Datasheet PDF下载

73S1121F-CGV/F图片预览
型号: 73S1121F-CGV/F
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller,]
分类和应用: 微控制器
文件页数/大小: 25 页 / 744 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
 浏览型号73S1121F-CGV/F的Datasheet PDF文件第1页浏览型号73S1121F-CGV/F的Datasheet PDF文件第3页浏览型号73S1121F-CGV/F的Datasheet PDF文件第4页浏览型号73S1121F-CGV/F的Datasheet PDF文件第5页浏览型号73S1121F-CGV/F的Datasheet PDF文件第6页浏览型号73S1121F-CGV/F的Datasheet PDF文件第7页浏览型号73S1121F-CGV/F的Datasheet PDF文件第8页浏览型号73S1121F-CGV/F的Datasheet PDF文件第9页  
73S1121F  
EMV Smart-Card Terminal Controller  
with Built-in Dual ISO-7816 Interface and USB  
DATA SHEET  
FEATURES  
80C52 core:  
Communication with smart cards:  
12 clock-cycle / instruction  
CPU clocked up to 24MHz (with a 12MHz crystal)  
ISO-7816 UART 9600 to 115kbps (with 12MHz  
crystal) for protocols T=0, T=1  
16-bit PC (64kB program linear memory address  
2-Byte FIFO for transmit and receive  
space)  
Hardware support to manage additional external  
card interfaces  
Memory:  
64kB internal Flash (Program Memory)  
128 Bytes Flash Info Memory Block  
Flash memory guaranteed for 10,000 erase-write  
cycles  
1kB IRAM (internal RAM for registers) + 4kB  
internal XRAM (User Data Memory)  
-
-
-
-
Control (16B FIFO)  
Interrupt IN (32B FIFO)  
Bulk IN (128B FIFO)  
Bulk OUT (128B FIFO)  
Interface for external program / data memory  
Boot-ROM loader program allows both In-System-  
Programming and In-Application-Programming of  
the embedded flash (ISP and IAP modes)  
ISP programming mode and external memory  
interface can be permanently disabled by protection  
fuses  
Man-Machine Interface and I/Os:  
5x6 Keyboard (hardware scanning, debouching and  
scrambling)  
Oscillators:  
(7) Dedicated LCD I/Os (Control of any external  
HD44780 standard LCD driver) – Can be also used  
as standard I/Os  
(8) User I/Os  
(4) GPIOs (with separate voltage reference input)  
Single low-cost 12MHz crystal  
Optional low-cost 32kHz crystal (with internal  
counter for RTC support)  
An Internal PLL provides all the necessary clocks to  
each block of the system  
Voltage Detection:  
Interrupts:  
(3) Analog Inputs (Voltage detection range: 0.2V to  
Standard 80C52 2-priority level structure  
8 different sources of interrupt  
2.5V)  
(1) 2.5V Voltage reference available on an output  
pin.  
Power Down Modes:  
2 standard 80C52 Power Down and IDLE modes  
1 low-speed mode (CPU run at 32kHz)  
Timers:  
Operating Temperature:  
(3) Standard 80C52 timers T0, T1 and T2  
0°C to 85°C  
(1) 16-bit timer that can generate RTC interrupts  
Package:  
from the 32KHz oscillator  
128 pin TQFP  
Bare Die  
(2) Built-in ISO-7816 card interfaces:  
(2) Independent step-up converters generate VCC  
Software:  
for the card (3V or 5V)  
Two-level Application Programming Interface (ANSI  
Compliant with EMV 4.0 (EMV2000)  
Activation/Deactivation sequencers  
Auxiliary I/O lines (C4-C8 signals)  
4.5kV ESD protection on all interface pins  
C-language libraries)  
USB, T=0/T=1 and EMV-compliant smart card  
protocol layers  
PIN Management functions compatible with CCID  
requirements  
Page: 2 of 25  
© 2005 TERIDIAN Semiconductor Corporation  
Rev 2.3