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73S1113F-CGT 参数 Datasheet PDF下载

73S1113F-CGT图片预览
型号: 73S1113F-CGT
PDF下载: 下载PDF文件 查看货源
内容描述: [USB Bus Controller, CMOS, PQFP64, LQFP-64]
分类和应用: 时钟数据传输外围集成电路
文件页数/大小: 19 页 / 366 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73S1113F  
EMV Smart-Card Terminal Controller  
with Built-in ISO-7816 Interface and USB  
DATA SHEET  
MICROCONTROLLER  
The 73S1113F core is an 8-bit 80C52 micro-controller, with embedded 5kB of RAM (data memory) and 64kB of  
flash (program memory). An additional Information Block Flash cell (128B IFB) is available for storage of device  
ID, serial number, firmware version etc.  
An embedded ROM boot-loader allows downloading of the flash memory (either program or IFB) through the  
serial port. This programming mode can be forced externally (In-System-Programming = ISP mode) or also can  
be called by the application (In-Application-Programming = IAP mode) through the Application Programming  
Interface. The 73S1113F flash memory can also be programmed with a parallel PROM programmer. Embedded  
security fuses allow the user to permanently disable the ISP mode. It allows the 73S1113F, once programmed  
with an application, to run independently without possibility from the external world to re-download a non-  
authorized application. Other features include:  
The 73S1113F has an on-chip oscillator that requires a 12MHz crystal. Internal clock circuitry generates  
clock signals to the different blocks and to the CPU (that can be clocked at 6, 12 or 24MHz).  
The 73S1113F has the standard 8052 2-priority level interrupt structure, with 8 different interrupt sources:  
2 external interrupts (pins INT2 and INT0), 3 timer interrupts, 1 serial/USB interrupt, 1 smart-card interrupt  
and a shared interrupt (keypad and analog comparator inputs).  
The 73S1113F incorporates 3 timers, T0, T1 and T2 that can be clocked internally or externally by the  
respective input signals on the pins USR0, USR1 and USR2.  
Standard 8052 Power Down mode and IDLE mode are supported for power saving modes. The clock for  
each block, as well as the analog circuitry (analog input, voltage reference and USB transceiver) and the  
DC-to-DC converter (VCC generator for the card) can be independently enabled or disabled by firmware  
to optimize power consumption.  
Management of the embedded card interface, peripherals and communication capabilities are controlled  
by means of dedicated registers in RAM. Management of the interrupts, of the power saving modes and  
of the clock circuitry is also controlled through registers.  
ISO-7816 INTERFACE AND UART  
The feature set of the TERIDIAN 73S1113F includes one built-in smart-card interface, controlled by an ISO-7816  
compliant sequencer. The built-in smart card interface has a DC-DC converter, which is able to generate the card  
power supply, VCC=3V or 5V. The sequencer handles the activation / deactivation of the card signals. The card  
interface includes an input for the card presence switch (programmable polarity) and auxiliary I/O lines for C4 / C8  
signals. A hardware ISO-7816 UART with a dedicated FIFO allows easy implementation of asynchronous card  
protocols T=0 and T=1. This UART can be bypassed to allow a firmware UART to handle other protocols such as  
synchronous card protocols. Control and use of the ISO-7816 UART is widely and easily configurable with  
dedicated registers located in XRAM. A 2-line interface enables the 73S1113F to control additional external  
smart card (ICC) interfaces, typically for multiple-SAM configurations. The ISO-7816 UART is shared between all  
the smart card interfaces (internal and external).  
COMMUNICATION, HUMAN-MACHINE INTERFACE AND I/Os  
The 73S1113F has a full-speed (12Mbps) USB slave interface with 4 endpoints for implementation of  
computer-connected terminals. A standard 8052 serial UART allows the 73S1113F to communicate with  
any host or peripheral on a serial link, at a data transmission rate from 1200 to 115kbps. Communication  
with a computer through RS232 can be easily implemented only using an external level shifter.  
Keyboard implementation is supported with a built-in 5x5 keyboard interface with hardware scanning and  
debouching. It also features a scrambling capability (change of the scanning order).  
7 I/O lines are dedicated to control an external standard LCD driver, allowing a wide choice of LCDs to be  
controlled by the 73S1113F, such as 7-wire, Hitachi-type HD44780.  
Additional input/outputs feature 8 user I/Os and 1 analog input for voltage detection (for battery  
monitoring or any DC voltage comparison).  
Page: 4 of 19  
© 2005 TERIDIAN Semiconductor Corporation  
Rev 2.3