73M1822/73M1922 Data Sheet
DS_1x22_001
Figures
Figure 1: Simple 73M1x22 Reference Block Diagram.................................................................................. 6
Figure 2: 73M1902 20-Pin TSSOP Pinout................................................................................................... 8
Figure 3: 73M1912 20-Pin TSSOP Pinout................................................................................................. 10
Figure 4: 73M1902 32-Pin QFN Pinout ..................................................................................................... 11
Figure 5: 73M1912 32-Pin QFN Pinout ..................................................................................................... 13
Figure 6: 73M1822 42-Pin Pinout.............................................................................................................. 15
Figure 7: MAFE Timing Diagram............................................................................................................... 19
Figure 8: Call Progress Monitor Frequency Response............................................................................... 20
Figure 9: Demo Board Circuit Connecting AOUT to a Speaker.................................................................. 20
Figure 10: Recommended Circuit for the 73M1922 ................................................................................... 28
Figure 11: Recommended Circuit for the 73M1822 ................................................................................... 29
Figure 12: Suggested Over-voltage Protection and EMI Suppression Circuit............................................. 31
Figure 13: Clock Generation Block Diagram (assumes 8 kHz sample rate) ............................................... 41
Figure 14: Crystal Oscillator with Configurable Load Current..................................................................... 41
Figure 15: Prescaler Block Diagram.......................................................................................................... 42
Figure 16: PLL Block Diagram .................................................................................................................. 42
Figure 17: Serial Port Timing Diagram ...................................................................................................... 46
Figure 18: Data and Control Frames Timing Diagram................................................................................ 47
Figure 19: Control Frame Position versus SPOS....................................................................................... 48
Figure 20: SCLK and FS with SCKM = 0................................................................................................... 48
Figure 21: Example Connections for Master and Slave Operation ............................................................. 49
Figure 22: Master/Slave Serial Timing Diagram ........................................................................................ 49
Figure 23: Daisy Chaining a Master and Two Slaves ................................................................................ 50
Figure 24: Timing Diagram with One Master and Two Slaves.................................................................... 50
Figure 25: Transmit Path Overall Frequency Response to Fs (8 kHz)........................................................ 52
Figure 26: Pass-Band Response of the Transmit Path .............................................................................. 52
Figure 27: Transmit Spectrum to 32 kHz................................................................................................... 53
Figure 28: Overall Frequency Response of the Receive Path.................................................................... 54
Figure 29: Pass-band Response of the Overall Receive Path.................................................................... 54
Figure 30: Line-Side Device AC and DC Circuits....................................................................................... 60
Figure 31: DC-IV Characteristics............................................................................................................... 61
Figure 32: Tip-Ring Voltage versus Current Using Different DCIV Settings................................................ 62
Figure 33: Voltage versus Current in the Seize Mode is the Same for All DCIV Settings............................ 63
Figure 34: Magnitude Response of IPMF, ACZ=01 (ETSI ES 203 021-2).................................................. 64
Figure 35: Magnitude Response of Billing Tone Notch Filter ..................................................................... 64
Figure 36: Loopback Modes Highlighted ................................................................................................... 75
Figure 37: Off-Hook Tip and Ring DC Characteristics................................................................................ 77
Figure 38: ES 203 021-2 DC Mask with Current Limit Enabled.................................................................. 77
Figure 39: Australian Hold State Characteristics ....................................................................................... 78
Figure 40: Return Loss .............................................................................................................................78
Figure 41: 20-Pin TSSOP Package Dimensions........................................................................................ 79
Figure 42: 32-Pin QFN Package Dimensions............................................................................................ 79
Figure 43: 42-Pin QFN Package Dimensions............................................................................................ 80
4
Rev. 1.6
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
