73M1903 Data Sheet
DS_1903_032
2 Control and Status Registers
Table 2 shows the memory map of addressable registers in the 73M1903. Each register and its bits are
described in detail in the following sections.
Table 2: Memory Map
Address Default Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
08h
00h
FFh
FFh
00h
00h
10h
00h
00h
0Ah
22h
12h
00h
C0h
00h
ENFE
TMEN
Unused
DIGLB
TXBST1 TXBST0 TXDIS
RXG1
RXG0
RXGAIN
HC
01
ANALB
GPIO 5
DIR5
INTLB
Reserved RXPULL SPOS
02
GPIO7 GPIO 6
DIR7 DIR6
GPIO 4 GPIO 3 GPIO 2 GPIO 1 GPIO 0
DIR4 DIR3 DIR2 DIR1 DIR0
03
04
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
05
06
Rev3
Rev2
Rev1
Rev0
Unused Reserved Reserved Reserved
07
Unused Reserved Reserved Reserved Reserved Reserved Reserved Reserved
08
Pseq7
Prst2
Ichp3
Pseq6
Prst1
Ichp2
Pseq5
Prst0
Pseq4
Pdvsr4
Ichp0
Pseq3
Pdvsr3
FL
Pseq2
Pdvsr2
Kvco2
Ndvsr2
Nseq2
Pseq1
Pdvsr1
Kvco1
Ndvsr1
Nseq1
Nrst1
Pseq0
Pdvsr0
Kvco0
Ndvsr0
Nseq0
Nrst0
09
0A
0B
0C
0D
0E
0E-7F
Ichp1
Unused Ndvsr6
Ndvsr5
Nseq5
Ndvsr4
Nseq4
Ndvsr3
Nseq3
Nseq7
Xtal1
Nseq6
Xtal0
Reserved Reserved Unused Nrst2
Frcvco PwdnPLL Reserved Unused Unused Unused Unused Unused
Unused Unused Unused Unused Unused Unused Unused Unused
To prevent unintended operation, do not write to reserved or unused locations. These locations are for
factory test or future use only and are not intended for customer programming.
8
Rev. 2.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
