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73M1903-IM/F 参数 Datasheet PDF下载

73M1903-IM/F图片预览
型号: 73M1903-IM/F
PDF下载: 下载PDF文件 查看货源
内容描述: 调制解调器模拟前端 [Modem Analog Front End]
分类和应用: 调制解调器
文件页数/大小: 46 页 / 530 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73M1903 Data Sheet  
DS_1903_032  
1 Signal Description  
The Teridian 73M1903 modem AFE IC is available in a 20-pin TSSOP or 32-pin QFN package with the  
same pin out. The following table describes the function of each pin. There are two pairs of power  
supply pins, VPA (analog) and VPD (digital). They should be separately decoupled from the supply  
source in order to isolate digital noise from the analog circuits internal to the chip. Failure to adequately  
isolate and decouple these supplies will compromise device performance.  
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles  
32QFN  
Pin #  
20VT  
Pin#  
Pin Name  
Type  
Description  
VND  
GND  
GND  
PWR  
PWR  
PWR  
PWR  
1,22  
16  
2,18 Negative Digital Ground  
VNA  
13  
3
Negative Analog Ground  
VPD  
2,25  
10  
Positive Digital Supply  
VPA  
8
Positive Analog Supply  
VPPLL  
VNPLL  
20  
17  
14  
Positive PLL Supply, shared with VPD  
Negative PLL Ground  
17  
Master reset. When this pin is a logic 0 all registers are  
reset to their default states; Weak-pulled high- default.  
RST  
I
9
7
Crystal oscillator input. When providing an external clock  
source, drive OSCIN.  
OSCIN  
I
19  
18  
16  
15  
OSCOUT  
O
Crystal oscillator circuit output pin.  
3, 4, 5, 6,  
23,  
Software definable digital input/output pins. Not available in  
the 20VT (TSSOP) package.  
GPIO(0-7)  
I/O  
N/A  
24,30,31  
VREF  
RXAP  
RXAN  
TXAP  
TXAN  
O
I
13  
15  
14  
12  
11  
6
Reference voltage pin (Reflects VREF).  
Receive analog positive input.  
12  
11  
10  
9
I
Receive analog negative input.  
Transmit analog positive output.  
Transmit analog negative output.  
O
O
Serial interface clock. With SCLK continuous selected,  
Frequency = 256*Fs ( =2.4576 MHz for Fs=9.6 kHz)  
SCLK  
O
8
5
SDOUT  
SDIN  
O
I
32  
29  
1
Serial data output (or input to the host).  
Serial data input (or output from the host).  
20  
4
Frame synchronization. (Active Low)  
FS  
O
I
7
19  
Type of frame sync. Open, weak-pulled high = early  
(mode1); tied low = late (mode0).  
TYPE  
27  
Controls the SCLK behavior after FS. Open, weak-pulled  
high = SCLK Continuous; tied low = 32 clocks per R/W  
cycle. Not available in 20VT.  
SckMode  
I
28  
NA  
4
Rev. 2.0