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73K324L 参数 Datasheet PDF下载

73K324L图片预览
型号: 73K324L
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片调制解调器 [Single-Chip Modem]
分类和应用: 调制解调器
文件页数/大小: 30 页 / 239 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73K324L  
CCITT V.22bis,V.23,V.22,V.21, Bell 212A  
Single-Chip Modem  
DATA SHEET  
internal state. DR is a detect register which provides  
an indication of monitored modem status conditions.  
TR, the tone control register, controls the DTMF  
generator, answer, guard tones, SCT, calling tone,  
and RXD output gate used in the modem initial  
connect sequence. CR2 is the primary DSP control  
interface and CR3 controls transmit attenuation and  
receive gain adjustments. All registers are read/write  
except for DR and ID, which are read only. Register  
control and status bits are identified below:  
REGISTER DESCRIPTIONS  
Eight 8-bit internal registers are accessible for  
control and status monitoring. The registers are  
accessed in read or write operations by addressing  
the A0, A1 and A2 address lines in Serial mode, or  
the AD0, AD1 and AD2 lines in Parallel mode. The  
address lines are latched by ALE. Register CR0  
controls the method by which data is transferred  
over the phone line. CR1 controls the interface  
between the microprocessor and the 73K324L  
REGISTER BIT SUMMARY  
ADDRESS  
DATA BIT NUMBER  
REGISTER  
CONTROL  
REGISTER  
0
AD - A0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
TRANSMIT  
MODE  
2
TRANSMIT  
MODE  
1
TRANSMIT  
MODE  
0
MODULATION MODULATION  
TRANSMIT  
ENABLE  
ANSWER/  
ORIGINATE  
MODULATION  
OPTION  
000  
CR0  
CR1  
DR  
TYPE  
1
TYPE  
0
BYPASS  
SCRAMBLER/  
ADD PH. EQ.  
(V.23)  
CONTROL  
REGISTER  
1
TRANSMIT  
PATTERN  
1
TRANSMIT  
PATTERN  
0
ENABLE  
DETECT  
INTERRUPT  
TEST  
MODE  
1
TEST  
MODE  
0
CLK  
CONTROL  
001  
010  
011  
100  
101  
101  
110  
RESET  
CALL  
PROGRESS  
DETECT  
SPECIAL  
TONE  
DETECT  
UNSCR.  
MARK  
DETECT  
DETECT  
REGISTER  
RECEIVE  
LEVEL  
PATTERN  
S1 DET  
RECEIVE  
DATA  
SIGNAL  
QUALITY  
CARRIER  
DETECT  
TRANSMIT  
GUARD TONE/  
SCT/CALLING  
TONE  
RXD  
OUTPUT  
CONTROL  
TRANSMIT  
ANSWER  
TONE  
DTMF0/GUARD/  
ANSWER/  
CALLING/SCT  
TONE  
CONTROL  
REGISTER  
DTMF2/  
4 WIRE FDX  
DTMF1/  
OVERSPEED  
TRANSMIT  
DTMF  
DTMF3  
TR  
CONTROL  
REGISTER  
2
SPECIAL  
REGISTER  
ACCESS  
TRANSMIT  
S1  
TRAIN  
INHIBIT  
EQUALIZER  
ENABLE  
CALL  
INITIALIZE  
RESET  
DSP  
CR2  
CR3  
SR  
0
16 WAY  
CONTROL  
REGISTER  
3
RECEIVE  
GAIN  
BOOST  
TRANSMIT  
ATTEN.  
3
TRANSMIT  
ATTEN.  
2
TRANSMIT  
ATTEN.  
1
TRANSMIT  
ATTEN.  
0
TRISTATE  
TX/RXCLK  
TXDALT  
0
TXD  
SOURCE  
SQ  
SELECT 1  
SQ  
SELECT 0  
SPECIAL  
REGISTER  
0
1
0
0
0
TX BAUD  
CLOCK  
RX UNSCR.  
DATA  
ID  
X
X
X
X
ID  
1
1
REGISTER  
NOTE: When a register containing reserved control bits is written into, the reserved bits must be programmed as  
0's.  
X = Undefined, mask in software.  
Page: 6 of 30  
© 2005, 2008 TERIDIAN Semiconductor Corporation  
Rev 7.1