73K324BL
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
SERIAL CONTROL INTERFACE MODE
FUNCTIONAL DESCRIPTION (continued)
The serial Command mode allows access to the
73K324BL control and status registers via a serial
control port. In this mode the AD0, AD1, and AD2
lines provide register addresses for data passed
through the AD7 (DATA) pin under control of the RD
and WR lines. A read operation is initiated when the
RD line is taken low. The next eight cycles of EXCLK
will then transfer out eight bits of the selected address
location LSB first. A write takes place by shifting in
eight bits of data LSB first for eight consecutive
cycles of EXCLK. WR is then pulsed low and data
transfer into the selected register occurs on the rising
edge of WR.
The synch/asynch converter also has an extended
Overspeed mode, which allows selection of an output
overspeed range of either +1% or +2.3%. In the
extended overspeed mode, stop bits are output at 7/8
rising edge of TXCLK the normal width.
Both the synch/asynch rate converter and the data
descrambler are automatically bypassed in the FSK
modes.
SYNCHRONOUS MODE
Synchronous operation is possible only in the QAM or
DPSK modes. Operation is similar to that of the
asynchronous mode except that data must be
synchronized to a provided clock and no variation in
data transfer rate is allowable. Serial input data
appearing at TXD must be valid on the rising edge of
TXCLK.
DTMF GENERATOR
The DTMF generator controls the sending of the
sixteen standard DTMF tone pairs. The tone pair sent
is determined by selecting transmit DTMF (bit D4)
and the 4 DTMF bits (D0-D3) of the Tone Register.
Transmission of DTMF tones from TXA is gated by
the transmit enable bit of CR0 (bit D1) as with all
other analog signals.
TXCLK is an internally derived 1200 or 2400 Hz
signal in internal mode and is connected internally to
the RXCLK pin in slave mode. Receive data at the
RXD pin is clocked out on the falling edge of RXCLK.
The asynch/synch converter is bypassed when
synchronous mode is selected and data is transmitted
at the same rate as it is input.
PARALLEL BUS CONTROL INTERFACE MODE
Eight 8-bit registers are provided for control, option
select, and status monitoring. These registers are
addressed with the AD0, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a
control microprocessor as seven consecutive memory
locations. Six control registers are read/write memory.
The detect and ID registers are read only and cannot
be modified except by modem response to monitored
parameters.
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© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 6.1
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