73K324BL
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
of monitored modem status conditions. TR, the tone
control register, controls the DTMF generator,
answer and guard tones and RXD output gate used
in the modem initial connect sequence. CR2 is the
primary DSP control interface and CR3 controls
transmit attenuation and receive gain adjustments.
All registers are read/write except for DR and ID,
which are read only. Register control and status bits
are identified below:
REGISTER DESCRIPTIONS
Eight 8-bit internal registers are accessible for
control and status monitoring. The registers are
accessed in read or write operations by addressing
the AD0, AD1 and AD2 lines in serial mode, or in
parallel mode. The address lines and CS are latched
by ALE in the parallel mode. Register CR0 controls
the method by which data is transferred over the
phone line. CR1 controls the interface between the
microprocessor and the 73K324BL internal state.
DR is a detect register which provides an indication
REGISTER BIT SUMMARY
ADDRESS
REGISTER
CONTROL
AD-A0
000
D7
D6
D5
D4
D3
D2
D1
D0
MODULATION
OPTION
MODULATION
MODULATION
TRANSMIT
MODE
2
TRANSMIT
MODE
TRANSMIT
MODE
TRANSMIT
ENABLE
ANSWER/
ORIGINATE
REGISTER
0
CR0
CR1
DR
TYPE
1
TYPE
0
1
0
CONTROL
REGISTER
1
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTERRUPT
BYPASS
SCRAMBLER
CLK
CONTROL
RESET
TEST MODE
1
TEST MODE
0
001
010
011
100
101
DETECT
REGISTER
RECEIVE
LEVEL
PATTERN
S1 DET
RECEIVE
DATA
UNSCR.
MARK
DETECT
CARRIER
DETECT
SPECIAL
TONE
DETECT
CALL
PROGRESS
DETECT
SIGNAL
QUALITY
TONE
RXD
OUTPUT
CONTROL
TRANSMIT
GUARD
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
DTMF 3
16 WAY
DTMF2/
4W/FDX
DTMF1/
EXTENDED
OVERSPEED
DTMF0/
GUARD/
ANSWER
CONTROL
REGISTER
TR
CONTROL
REGISTER
2
SPECIAL
REGISTER
ACCESS
CALL
INITIALIZE
TRANSMIT
S1
RESET
DSP
TRAIN
INHIBIT
EQUALIZER
ENABLE
CR2
CR3
0
CONTROL
REGISTER
3
TXDALT
TRISTATE
TX/RXCLK
RECEIVE
GAIN
BOOST
TRANSMIT
ATTEN.
3
TRANSMIT
ATTEN.
2
TRANSMIT
ATTEN.
1
TRANSMIT
ATTEN.
0
OH
SPECIAL
REGISTER
TX BAUD
CLOCK
RX UNSCR.
DATA
TXD
SOURCE
SQ
SELECT 1
SQ
SELECT 0
SR
ID
101
110
0
0
0
1
ID
REGISTER
ID
ID
ID
ID
X
X
X
NOTE: When a register containing reserved control bit is written into, the reserved bits must be programmed as
0’s.
X = Undefined, mask in software
Page: 9 of 34
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 6.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
