欢迎访问ic37.com |
会员登录 免费注册
发布采购

73K224L-28IHR/F 参数 Datasheet PDF下载

73K224L-28IHR/F图片预览
型号: 73K224L-28IHR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片调制解调器 [Single-Chip Modem]
分类和应用: 调制解调器电信集成电路电信电路
文件页数/大小: 31 页 / 243 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
 浏览型号73K224L-28IHR/F的Datasheet PDF文件第1页浏览型号73K224L-28IHR/F的Datasheet PDF文件第2页浏览型号73K224L-28IHR/F的Datasheet PDF文件第3页浏览型号73K224L-28IHR/F的Datasheet PDF文件第4页浏览型号73K224L-28IHR/F的Datasheet PDF文件第6页浏览型号73K224L-28IHR/F的Datasheet PDF文件第7页浏览型号73K224L-28IHR/F的Datasheet PDF文件第8页浏览型号73K224L-28IHR/F的Datasheet PDF文件第9页  
73K224L  
V.22bis, V.22, V.21, Bell 212A, 103  
Single-Chip Modem  
DATA SHEET  
DTE USER INTERFACE  
NAME  
TYPE DESCRIPTION  
EXCLK  
I
External Clock. This signal is used in synchronous transmission when the  
external timing option has been selected. In the external timing mode the rising  
edge of EXCLK is used to strobe synchronous transmit data available on the  
TXD pin. Also used for serial control interface.  
RXCLK  
O/  
Receive Clock. Tri stateable. The falling edge of this clock output is coincident  
Tristate with the transitions in the serial received data output. The rising edge of RXCLK  
can be used to latch QAM or DPSK valid output data. RXCLK will be active as  
long as a carrier is present.  
RXD  
O/  
Received Digital Data Output. Serial receive data is available on this pin. The  
Weak data is always valid on the rising edge of RXCLK when in synchronous mode.  
Pull-up RXD will output constant marks if no carrier is detected.  
TXCLK  
O/  
Transmit Clock. Tri stateable. This signal is used in synchronous transmission to  
Tristate latch serial input data on the TXD pin. Data must be provided so that valid data is  
available on the rising edge of the TXCLK. The transmit clock is derived from  
different sources depending upon the synchronization mode selection. In Internal  
Mode the clock is generated internally. In External Mode TXCLK is phase locked  
to the EXCLK pin. In Slave Mode TXCLK is phase locked to the RXCLK pin.  
TXCLK is always active.  
TXD  
I
Transmit Digital Data Input. Serial data for transmission is input on this pin. In  
synchronous modes, the data must be valid on the rising edge of the TXCLK  
clock. In asynchronous modes (2400/1200/600 bit/s or 300 baud) no clocking is  
necessary. DPSK data must be +1%, -2.5% or +2.3%, -2.5 % in extended  
overspeed mode.  
ANALOG INTERFACE AND OSCILLATOR  
RXA  
TXA  
I
O
I
Received modulated analog signal input from the phone line.  
Transmit analog output to the phone line.  
XTL1  
XTL2  
These pins are for the internal crystal oscillator requiring a 11.0592 MHz parallel  
mode crystal. Two capacitors from these pins to ground are also required for  
proper crystal operation. Consult crystal manufacturer for proper values. XTL2  
can also be driven from an external clock.  
I/O  
Page: 5 of 31  
© 2005, 2008 TERIDIAN Semiconductor Corporation  
Rev 7.1