71M6521DE/71M6521FE
Energy Meter IC
DATASHEET
JANUARY 2008
VREF
V3P3A
GNDA
V3P3SYS
ΔΣ ADC
CONVERTER
IA
VA
IB
V3P3D
VBIAS
V3P3A
MUX
VBIAS
VREF
VB
V3P3D
VBAT
-
VBAT
TEMP
+
FIR
ADC_E
VBAT
VREF
FIR_LEN
VREF_CAL
VREF_DIS
MUX
MUX
CTRL
CROSS
EQU
MUX_ALT
CK32
VOLT
REG
CHOP_E
MUX_DIV
X4MHZ
XIN
OSC
(32KHz)
MCK
PLL
DIV
ADC
RTCLK(32KHz)
CK32
GNDD
V2P5
LCD_ONLY
SLEEP
32KHz
XOUT
CKADC
4.9MHz
CKOUT_E
CKFIR
4.9MHz
CKTEST/
SEG19
4.9MHz
2.5V to logic
CKOUT_E
V3P3D
CK_GEN
CK_2X
LCD_GEN
VLC2
ECK_DIS
MPU_DIV
VLC1
VLC0
CE RAM
(0.5KB)
LCD_MODE
LCD_E
MUX_SYNC
CKCE
STRT
WPULSE
VARPULSE
RTM
MUX
CE
LCD DISPLAY
DRIVER
<4.9MHz
DATA
00-7F
32 bit Compute
Engine
TEST
MODE
MEMORY SHARE
TEST
COM0..3
SEG0..18
LCD_NUM
LCD_MODE
LCD_CLK
LCD_E
LCD_BLKMAP
LCD_SEG
LCD_Y
PROG
000-7FF
SEG32,33
SEG19,38
CE
CONTROL
1000-11FF
SEG24/DIO4 ..
SEG31/DIO11
RTM_0..3
RTM_E
CE_E
SEG34/DIO14 ..
SEG37/DIO17
DIGITAL I/O
PLS_INV
DIO_EEX
DIO_PV/PW
DIO_DIR
DIO_R
LCD_NUM
DIO
WPULSE
PLS_INTERVAL
PLS_MAXWIDTH
CE_LCTN
EQU
PRE_SAMPS
SUM_CYCLES
VARPULSE
DIO1,2
EEPROM
INTERFACE
PB
RTC
RTCLK
RTC_DEC_SEC
RTC_INC_SEC
CKMPU
<4.9MHz
CONFIGURATION
PARAMETERS
SDCK
SDOUT
SDIN
CONFIG
RX
TX
(68PinPackageOnly)
DIO3,
UART
2000-20FF
DATA
DIO19/SEG39,
DIO20/SEG40,
DIO21/SEG41
0000-FFFF
MPU
(80515)
OPT_RX/
DIO1
0000-07FF
MPU XRAM
(2KB)
OPTICAL
0000-
7FFF
OPT_TX/
DIO2/
WPULSE/
VARPULSE
FLASH
(16/32KB)
MOD
OPT_RXDIS
OPT_RXINV
PROG
0000-7FFF
MEMORY
SHARE
CE_LCTN
OPT_TXMOD OPT_TXE
OPT_FDC
OPT_TXINV
FLSH66ZT
VBIAS
MPU_RSTZ
EMULATOR
PORT
POWER FAULT
WAKE
FAULTZ
V1
TEST
MUX
TMUXOUT
E_RXTX
E_TCLK
E_RST (Open Drain)
COMP_STAT
TMUX[4:0]
December 11, 2006
E_RXTX/SEG38
E_TCLK/SEG33
E_RST/SEG32
RESET
ICE_E
Figure 1: IC Functional Block Diagram
Page: 8 of 101
© 2005-2008 TERIDIAN Semiconductor Corporation
v1.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
