71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
Figure 27: Meter Accuracy over Harmonics at 240V, 30A .............................................................................75
Figure 28: Typical Meter Accuracy over Temperature Relative to 25°C (w/ Temperature
Compensation) .....................................................................................................................75
Figure 29: Resistive Voltage Divider (left), Current Transformer (right) .........................................................76
Figure 30: Resistive Shunt (left), Rogowski Coil (right)..................................................................................76
Figure 31: Crystal Frequency over Temperature ...........................................................................................77
Figure 32: Crystal Compensation...................................................................................................................78
Figure 33: Connecting LCDs..........................................................................................................................79
Figure 34: LCD Boost Circuit .........................................................................................................................79
Figure 35: EEPROM Connection ...................................................................................................................80
Figure 36: Interfacing RX to a 0-5V Signal.....................................................................................................80
Figure 37: Connection for Optical Components .............................................................................................81
Figure 38: Voltage Divider for V1...................................................................................................................81
Figure 39: External Components for RESETZ...............................................................................................82
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles.............................................................8
Table 2: Channel control based on MUX_DIV and FIR_LEN...........................................................................9
Table 3: CE DRAM Locations for ADC Results .............................................................................................12
Table 4: Standard Meter Equations (inputs shown gray are scanned but not used for calculation) ...............12
Table 5: Stretch Memory Cycle Width............................................................................................................16
Table 6: Internal Data Memory Map...............................................................................................................17
Table 7: Special Function Registers Locations ..............................................................................................17
Table 8: Special Function Registers Reset Values ........................................................................................18
Table 9: PSW Register Flags.........................................................................................................................19
Table 10: PSW bit functions...........................................................................................................................19
Table 11: Port Registers ................................................................................................................................20
Table 12: Special Function Registers ............................................................................................................21
Table 13: Baud Rate Generation ...................................................................................................................22
Table 14: UART Modes .................................................................................................................................22
Table 15: The S0CON Register.....................................................................................................................22
Table 16: The S1CON register ......................................................................................................................23
Table 17: The S0CON Bit Functions..............................................................................................................23
Table 18: The S1CON Bit Functions..............................................................................................................24
Table 19: The TMOD Register.......................................................................................................................24
Table 20: TMOD Register Bit Description......................................................................................................25
Table 21: Timers/Counters Mode Description................................................................................................25
Table 22: The TCON Register .......................................................................................................................25
Table 23: The TCON Register Bit Functions..................................................................................................26
Table 24: Timer Modes..................................................................................................................................26
Table 25: The PCON Register.......................................................................................................................26
Table 26: The IEN0 Register (see also Table 34)..........................................................................................27
Table 27: The IEN0 Bit Functions (see also Table 34)...................................................................................27
Table 28: The IEN1 Register (see also Tables 35/36) ...................................................................................27
Table 29: The IEN1 Bit Functions (see also Tables 35/36)............................................................................27
Table 30: The IP0 Register (see also Table 46) ............................................................................................28
Table 31: The IP0 bit Functions (see also Table 46)......................................................................................28
Table 32: The WDTREL Register ..................................................................................................................28
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