78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit
Pulse Amplitude Adjustment
FUNCTIONAL DESCRIPTION (continued)
Controls for adjusting the transmit pulse amplitude
are provided in both hardware and software modes.
Amplitude boosts of 5% and 10% can be enabled by
the TXOUT0 pin or BST[1:0] register bits as follows:
Parallel Modes
In parallel modes, 4-bit CMOS data segments are
input to the chip with a 34.816MHz (E4) or
38.88MHz (STM1) clock. These inputs are passed
to the 4x8 decoupling FIFO and then to a serializer
for transmission. For maximum compatibility, the
78P2352 can operate in both slave and master clock
modes as shown in Figures 4 and 5 respectively. A
loop-timing mode is also available to allow external
remote loopbacks (i.e. line loopback in framer).
BST[1:0] bits
Amplitude
TXOUT0 pin
Low
Float
High
0 0
0 1
1 1
Normal
5% boost
10% boost
Clock Synthesizer
HW Control Pins
SDI_PAR CKMODE
SW Control Bits
Parallel
Mode
The transmit clock synthesizer is a low-jitter PLL that
generates a 278.528/311.04 MHz clock for the CMI
PAR
PMODE
encoder.
A synthesized 139.264/155.52 MHz
Slave
High
High
Low
1
0
reference clock is also used in both the receive and
transmit sides for clock and data recovery.
Slave +
Float
1
1
1
1
*Loop-timing
The 2x line rate clock is also available at the
TXCKxP/N pins for downstream synchronization or
interfacing to equipment lacking integrated clock
recovery.
Master
High
High
*Loop-timing in software mode requires SMOD[1:0]=11
Transmit Backplane Equalizer
Reference
Clock
An optional fixed equalizer is integrated in the
transmit path for architectures that use LIUs on
active interface cards. The fixed equalizer can
compensate for up to 1.5m of FR4 trace and can be
enabled by the TXOUT1 pin or TXEQ bit as follows:
CKREFP/N
PIx[3:0]D
PIxCK
CMI
CMI
Coax
Coax
4-bit CMOS TTL
34/39 MHz
CMIxP/N
RXxP/N
XFMR
XFMR
Framer/
Mapper
TDK
78P2352
POx[3:0]D
POxCK
4-bit CMOS TTL
34/39 MHz
TXEQ bit
Tx Equalizer
TXOUT1 pin
Low
Float
1
0
Enabled
Disabled
Figure 4: Slave Parallel Mode
Reference
Clock
Transmit Loss of Lock
In serial modes using the integrated CDR, the
78P2352 will declare a loss of lock condition when
the recovered transmit clock frequency differs from
the reference clock by more than 100ppm in an
CKREFP/N
PIx[3:0]D
PTOxCK
CMI
CMI
Coax
Coax
4-bit CMOS TTL
34/39 MHz
CMIxP/N
RXxP/N
XFMR
XFMR
Framer/
Mapper
TDK
78P2352
POx[3:0]D
POxCK
4-bit CMOS TTL
34/39 MHz
interval greater than 420µs.
This condition is
cleared when the frequencies are less than
100ppm off for more than 500µs.
Figure 5: Master Parallel Mode
Transmit Driver
POWER-DOWN FUNCTION
Power-down control is provided to allow the
78P2352 to be shut off. Transmit and receive
power-down can be set independently through SW
In CMI (electrical) mode, the CMIxP/N pins connect
the chip to 75Ω coaxial cable through a transformer
and termination resistors. The transmitter converts
the data to CMI coding and shapes an analog signal
to meet the appropriate ITU-T G.703 template. The
CMI outputs are tri-stated during transmit disable
control.
Global power-down is achieved by
powering down both the transmitter and receiver.
Note: the serial interface and configuration
registers are not affected by power-down.
and
transmit
power-down
for
redundancy
applications.
The transmitter can also be powered down using the
TXPD control pin. The CMI outputs are tri-stated
during transmit power-down for redundancy
When the CMI pin is low, the chip is in NRZ (optical)
mode. The output data signal from the ECLxP/N
pins have LVPECL levels and interface directly to a
fiber module. The CMI driver, encoder and decoder
are disabled in ECL (NRZ) mode.
applications.
The TXPD pin is active in both
hardware and software modes.
6
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