AVPro® 5002R
Dual SCART A/V Switch
DATA SHEET
SCART Audio Switching
The audio inputs are considered to be associated with
the respective video inputs. As a result, the video
selection determines which audio signals will be
switched to a given SCART output. Refer to the serial
port register table for more information. Also see the
audio switching block diagram shown in Figure 2.
TV SCART Audio Outputs: The first pair of signals is
labeled TV_Lout and TV_Rout on the block diagram.
TV_Lout and TV_Rout are typically used to drive the
TV SCART audio pins. These outputs also have an
internal multiplexer that allows the user to select TV
audio either before or after the internal volume control
function. When Bit 0 in Register 4 is set low (0), the
volume control is used. When this bit is set high (1),
the volume control is bypassed. The power-up default
state is volume control active.
The 5002R provides inputs for the auxiliary audio
source (Aux_Lin/Aux_Rin), a stereo DAC associated
with the video encoder inputs (Lin/Rin), and inputs from
the TV SCART (TV_Lin/TV_Rin).
TV Audio Operation
TV Audio Line Outputs: The second pair of signals is
labeled Lout and Rout on the block diagram. Lout and
Rout are standard line outputs. The Lout/Rout outputs
have an internal multiplexer that allows the user to
select TV audio either before or after the internal
volume control function. When Bit 1 in Register 4 is set
low (0), the volume control is used. When this bit is set
high (1), the volume control is bypassed. The power-up
default state is volume control active. In addition, the
audio inputs from the TV SCART connector
(TV_Lin/TV_Rin) can be switched to the line outputs.
This is controlled by bit-3 of Register 4. Setting this bit
low (0) is the normal operation where the line outputs
follow the TV SCART outputs. Setting this bit high (1)
will switch the line outputs to the audio source on the
TV_Lin/TV_Rin inputs.
The audio source for the TV port is selected in concert
with the video source using the three (3) LSBs of
Register 1. The selected audio signals are input to
internal multiplexers that allow the user to select
between mono and stereo output options. Bits 4 and 5
of Register
3 control the stereo/mono selection
according to the following table:
Bit 1
Bit 0
TV left source
left input
left + right
left input
TV right source
right input
left + right
0
0
1
1
0
1
0
1
left input
right input
right input
At power-up, these bits default to 00 putting the device
in the stereo mode.
RF Mono Output: The TV_Lout and TV_Rout signals
are also summed internally to generate a mono audio
signal for an external RF modulator. This output is
labeled Mod_Mono. The internal summing circuit is
after the volume control mux so the audio control on
this output will be the same as that selected for the
TV_Lout and TV_Rout outputs.
Volume Control: The left and right TV audio channels
can be selected to pass through volume control circuits.
Each volume control circuit is formed by a serially
connected amplifier and attenuator pair. The amplifier
is programmed by register 4, bit 2( “0” for 0 dB and “1”
for 6 dB gains ). The attenuator is programmed by the
lower 6 bits of register 0( “xx000000” for 0 dB and
“xx111111” for –63 dB attenuation, in –1 dB steps ).
TV Audio Mute: A mute function is provided for all TV
audio outputs. The mute function is controlled by
setting Bit 6 in Register 0. When this bit is set to a high
state (1), all TV audio outputs are muted. This will be
the default condition at power-up. When the bit is set to
a low state (0), the audio path will be in normal
operating mode. This bit can be set independent of the
volume control such that the outputs can be muted
before any change in volume, or any switching of audio
sources.
DAC Input Gain (Lin/Rin): To support audio DACs
that have a limited output range, the 5002R provides
programmable gain amplifiers on the Lin and Rin
inputs. The gain is set by Bits 2 and 3 of Register 3,
according to the following table:
Bit 3
Bit 2
Gain
0
0
1
1
0
1
0
1
Gain = 0 dB
Gain = 6 dB
Gain = 9 dB
Gain = 11.5 dB
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© 2008 TERIDIAN Semiconductor Corporation
Rev 2.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
