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5002R-CGT/F 参数 Datasheet PDF下载

5002R-CGT/F图片预览
型号: 5002R-CGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: 双SCART音频/视频开关 [Dual SCART A/V Switch]
分类和应用: 开关
文件页数/大小: 30 页 / 435 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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AVPro® 5002R  
Dual SCART A/V Switch  
DATA SHEET  
ELECTRICAL SPECIFICATIONS  
ABSOLUTE MAXIMUM RATINGS  
Operation beyond the maximum ratings may damage the device  
PARAMETER  
RATING  
Storage temperature  
-55 to 150 °C  
Junction operating temperature  
5V supply voltage pins  
+125 °C  
-0.3 V < VCC < 6 V  
-0.3 V < VDD < 13 V  
-0.3 V to VCC+0.3 V  
-0.3 V to VCC+0.3 V  
-0.3 V < VDD < 13 V  
-0.3 V < VDD < 13 V  
±5 kV  
12V supply pin  
Voltage applied to Digital and Video Inputs  
Voltage applied to video pins  
Voltage applied to audio pins  
Voltage applied to FNC pin (input)  
ESD tolerance – SCART pins*  
ESD tolerance – other pins  
±2.5 kV  
* Note: To pass the SCART 15 kV ESD requirement, external protection for the IC is required.  
SPECIFICATIONS: Unless otherwise specified: 0° < Ta < 70 °C; power supplies VCC = +5.0 V ±5%, VDD = 12.0 V  
±5%.  
PARAMETER  
CONDITION  
MIN  
NOM  
MAX  
UNIT  
Operating Characteristics  
Power Supply Currents  
(Default register setting)  
No signal, video outputs not loaded  
VCC (+5 VDC)  
VDD (+12 VDC)  
18  
17  
mA  
mA  
Power Supply Currents  
(Composite Auxiliary outputs on)  
No signal, video outputs not loaded  
VCC (+5 VDC)  
28  
20  
mA  
mA  
VDD (+12 VDC)  
PSRR  
f = 100 Hz, 0.3 Vpp on VCC/ VDD  
40  
dB  
in  
Switch time  
Serial Port Timing( Set by I2C controller )  
From rising edge of 8th clock  
0.8  
μs  
SCLK Input Frequency  
400  
kHz  
μs  
μs  
ns  
ns  
ns  
ns  
μs  
μs  
μs  
ns  
SCLK LOW time (tCL)  
1.3  
0.6  
SCLK HIGH time (tCH)  
Rise time (tRT)  
SCLK and SDATA  
300  
300  
Fall time (tFT)  
SCLK and SDATA  
Data set-up time* (tDSU)  
Data hold time* (tDH)  
Start set-up time (tSSU)  
Start hold time (tSH)  
Stop set-up time (tPSU)  
Glitch rejection  
SDATA change to SCLK HIGH  
SCLK LOW to SDATA change  
100  
30  
0.6  
0.6  
0.6  
maximum pulse on SCLK and/or  
50  
SDATA  
* These specifications also apply to an acknowledge generated by the device.  
Page: 15 of 30  
© 2008 TERIDIAN Semiconductor Corporation  
Rev 2.1  
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