Digital pulse compression module
CI F04 / CI F05 Compressor
Technical description
CI F04 compressor functional block diagram is featured on Fig. 1 while CI F05 block diagram is featured on Fig. 2.
FPGA
Waveform
selection
WF MS el_A
To
FIR
Filter
To
F0
IN_A
OUT_A
ADC
BaseBand
DAC
Sy stem
Clock
Power
Control
Power S upply
Superv ision
BITE
BOARD_OK
Connect
JTAG
Program
FPGA
Fig. 1 : CI F04 compressor functional block diagram
WFMSel_B
WFMSel_A
FPGA
Waveform
selection
To
FIR
To
F0
IN_B
IN_A
OUT_B
OUT_A
ADC
ADC
BaseBand
Filter
DAC
DAC
To
FIR
Filter
To
F0
BaseBand
System
Clock
Power
Control
Power Supply
Supervision
BITE
BOARD_OK
Connect
JTAG
Program
FPGA
Fig. 2 : CI F05 compressor functional block diagram
Input chirps are filtered (anti-aliasing filter), sampled and down-converted to baseband. I and Q baseband data
are processed by FIR filters whose coefficients are matched with the expander chirp characteristics. Digital
baseband I/Q compressed pulse is then up-converted to carrier frequency and converted into analog signal.
As inputs and outputs are IF analog signals, CI F0x are well suited to upgrade SAW based pulse compression
Radars. For better compatibility with old SAW based subsystems, an adjustable additional delay may be inserted.
CI F05 unit is able to process on-the-fly 2 independent and concurrent channels. Fig. 3 gives the maximum chirp
duration value vs. bandwidth achievable for each channel. Consider for B the maximum bandwidth value of the 2
waveforms, and for T the maximum time duration value of the 2 waveforms.
The internal low noise system clock is self-sufficient, and does not need to be referenced on any external clock.
CI F0x unit is provided with FPGA firmware loaded. Functions, and channels specifications (time dispersion,
compressed pulse width, side lobes level…) should be provided by customer; Rakon-Temex will customize the
FPGA program to fulfill customer requirements.
For each channel, waveform is selected among 2 possible waveforms, using WFMSel_x inputs, as presented in
Table 1 and Table 2. Each time WFMSel_x signal changes, the new set of waveform coefficients will be active 50
µs later.
CI F0x unit continuously monitors internal power supply and FPGA program integrity. If voltage exceeds nominal
levels, or if FPGA program is corrupted, BITE output is deasserted, and LED is turned off. The BITE output
indicates the GO-NOGO state of the compressor.
Oct 16th, 2015
CI F04 / CI F05 Compressor Revision A4
2 / 8
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TEMEX [ TEMEX ]
