5V PRECISION DATA ACQUISITION
SUBSYSTEMS
TC530
TC534
PIN DESCRIPTION (Cont.)
Pin No.
(TC530
28-Pin
Pin No.
(TC530
28-Pin
SOIC)
Pin No
(TC534
40-Pin
PDIP)
Pin No.
(TC534
44-Pin
PQFP)
PDIP, 300 Mil.)
Symbol Description
15
15
22
19
OSCIN
Analog Input. This pin connects to the other side of the
crystal described in OSCOUT above. The TC530/534 may also
be clocked from an external frequency source connected to
this pin. The external frequency source must be a pulse wave
form with a minimum 30% duty cycle and rise and fall times
15nsec (Max). If an external frequency source is used, OSCOUT
must be left floating. A maximum operating frequency of 2MHz
(crystal) or 4MHz (external clock source) is permitted.
16
17
16
17
23
24
20
21
DOUT
DCLK
Logic Level Output. Serial port data output pin. This pin is
enabled only when R/W is high.
Logic Input, Positive and Negative Edge Triggered. Serial port
clock. When R/W is high, serial data is clocked out of the
TC530/534A (on DOUT) at each HIGH-to-LOW transition of
D
CLK. A/D initialization data (LOAD VALUE) is clocked into the
TC530/534 (on DIN) at each LOW-to-HIGH transition of DCLK. A
maximum serial port DCLK frequency of 3MHz is permitted.
18
18
25
22
DIN
Logic Level Input. Serial port input pin. The A/D converter
integration time (TINT) and Auto Zero time (TAZ) values are
determined by the LOAD VALUE byte clocked into this pin.
This initialization must take place at power up, and can be
rewritten (or modified and rewritten) at any time. The LOAD
VALUE is clocked into DIN MSB first.
19
20
19
20
26
27
23
24
R/W
Logic Level Input. This pin must be brought low to perform a
write to the serial port (e.g. initialize the A/D converter). The
DOUT pin of the serial port is enabled only when this pin is high.
EOC
Open Drain Output. End-of-Conversion (EOC) is asserted
any time the TC530/534 is in the AZ phase of conversion. This
occurs when either the TC530/534 initiates a normal AZ phase,
or when RESET is pulled high. EOC is returned high when the
TC530/534 exits AZ. Since EOC is driven low immediately
following completion of a conversion cycle, it can be used as
a DATA READY processor interrupt.
21
21
30
28
RESET
Logic Level Input. It is necessary to force the TC530/534 into
the Auto Zero phase when power is initially applied. This is
accomplished by momentarily taking RESET high. Using an I/O
port line from the microprocessor, or by applying an external
system reset signal, or by connecting a 0.01µF capacitor from
the RESET input to VSS
.
Conversions are performed continuously as long as RESET is
low and conversion is halted when RESET is high. RESET
may therefore be used in a complex system to momentarily
suspend conversion (for example while the address lines of an
input multiplexer are changing state). In this case, RESET
should be pulled high only when the EOC is LOW to avoid
excessively long integrator discharge times which could result in
erroneous conversion (see Applications Section).
3-52
TELCOM SEMICONDUCTOR, INC.
TELCOM [ TELCOM SEMICONDUCTOR, INC ]
