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TC4468COE 参数 Datasheet PDF下载

TC4468COE图片预览
型号: TC4468COE
PDF下载: 下载PDF文件 查看货源
内容描述: 逻辑输入CMOS Quad驱动程序 [LOGIC-INPUT CMOS QUAD DRIVERS]
分类和应用: 输入元件驱动
文件页数/大小: 9 页 / 121 K
品牌: TELCOM [ TELCOM SEMICONDUCTOR, INC ]
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LOGIC-INPUT CMOS  
QUAD DRIVERS  
4
TC4467  
TC4468  
TC4469  
ELECTRICAL CHARACTERISTICS: Measured throughout operating temperature range with 4.5V VDD 18V,  
unless otherwise specified.  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Unit  
Input  
VIH  
Logic 1, High Input Voltage  
Logic 0, Low Input Voltage  
Input Current  
(Note 3)  
2.4  
0.8  
10  
V
VIL  
(Note 3)  
V
IIN  
0V VIN VDD  
– 10  
µA  
Output  
VOH  
VOL  
RO  
High Output Voltage  
Low Output Voltage  
Output Resistance  
Peak Output Current  
ILOAD = 100 µA (Note 1)  
ILOAD = 10 mA (Note 1)  
IOUT = 10 mA, VDD = 18V  
VDD – 0.025  
0.30  
30  
V
V
20  
1.2  
IPK  
A
I
Latch-Up Protection  
4.5V VDD 16V  
500  
mA  
Withstand Reverse Current  
Switching Time  
tR  
Rise Time  
Figure 1  
Figure 1  
Figure 1  
Figure 1  
50  
50  
nsec  
nsec  
nsec  
nsec  
tF  
Fall Time  
tD1  
Delay Time  
Delay Time  
100  
100  
tD2  
Power Supply  
IS  
IS  
Power Supply Current  
Power Supply Voltage  
8
mA  
V
Note 2  
4.5  
18  
NOTES: 1. Totem-pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to  
drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device.  
2. When driving all four outputs simultaneously in the same direction, VDD shall be limited to 16V. This reduces the chance that internal  
dv/dt will cause high-power dissipation in the device.  
3. The input threshold has about 50 mV of hysteresis centered at approximately 1.5V. Slow moving inputs will force the device to  
dissipate high peak currents as the input transitions through this band. Input rise times should be kept below 5 µs to avoid high internal  
peak currents during input transitions. Static input levels should also be maintained above the maximum or below the minimum input  
levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.  
PIN CONFIGURATIONS  
16-Pin SOIC (Wide)  
14-Pin Plastic DIP/CerDIP  
1A  
1B  
V
DD  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1A 1  
1B 2  
2A 3  
2B 4  
14 V  
DD  
V
DD  
13 1Y  
2A  
1Y  
2Y  
3Y  
4Y  
4B  
4A  
12 2Y  
11 3Y  
10 4Y  
2B  
TC4467/8/9  
TC4467/8/9  
3A  
3B  
3A 5  
3B 6  
GND  
GND  
9
8
4B  
4A  
GND 7  
TELCOM SEMICONDUCTOR, INC.  
4-263