CMOS CURRENT MODE
PWM CONTROLLERS
1
2
3
4
5
6
7
8
TC18C46
TC28C46
TC38C46
Peak Current Limit Setup
The input pulse to pin 16 should be at least 100nsec
wide and have an amplitude of at least 1V in order to get the
minimum propagation delay from input to output. If these
parameters are met, the delay should be less than 400nsec
at 25°C; however, the delay time will increase as the device
temperature rises.
Resistors R1 and R2 at the CURRENT LIMIT input (pin
1) set the peak current limit (Figure 1). The potential at pin
1 is easily calculated:
R2
V1 = VREF
R1 + R2
Soft Restart From Shutdown
R1 should be selected first. The shutdown circuit fea-
ture is not latched for (VREF – 0.35)/R1 <65µA and is latched
for currents greater than 140µA.
The error amplifier output voltage is clamped from
going above V1 through the limit buffer amplifier. Peak
current is sensed by RS and amplified by the current
amplifier which has a fixed gain of 3.
IPCL, the peak current limit, is the current that causes
the PWM comparator noninverting input to exceed V1, the
potential at the inverting input. Once the comparator trip
point is exceeded, both outputs are disabled.
A soft restart can be programmed if nonlatched shut-
down operation is used.
A capacitor at pin 1 will cause a gradual increase in
potential toward V1. When the voltage at pin 1 reaches
0.75V, the PWM latch set input is removed and the circuit
establishesaregulatedoutputvoltage. Thesoft-startopera-
tion forces the PWM output drivers to initially operate with
minimum duty cycle and low peak currents.
Even if a soft start is not required, it is necessary to
insert a capacitor between pin 1 and ground if the current IL
is greater than 140µA. This capacitor will prevent "noise
triggering" of the latch, yet minimize the soft-start effect.
IPCL is easily calculated:
V1 – 0.65V
IPCL
where:
V1 = VREF
=
Soft-Start Power-Up
3 (RS)
During power-up, a capacitor at R1, R2 initiates a soft-
start cycle. As the input voltage (pin 15) exceeds the
under-voltage lockout potential (7V), Q4 is turned OFF,
ending undervoltage lockout. Whenever the PWM com-
parator inverting input is below 0.65V, both outputs are
disabled.
When the undervoltage lockout start threshold is ex-
ceeded, the capacitor begins to charge. The PWM duty
cycleincreasesuntiltheoperatingoutputvoltageisreached.
Soft-startoperationforcesthePWMoutputdriverstoinitially
operate with minimum duty cycle and low peak current.
R2
R1 + R2
VREF = Internal voltage reference = 5.1V
3 = Gain of current-sense amplifier
0.65V = Current limit offset
Both driver OUTPUTs (pins 11 and 14) are OFF (LOW)
when the peak current limit is exceeded. When the sensed
current goes below IPCL, the circuit operates normally.
Current-Sense Amplifier
Output Shutdown
The current-sense amplifier operates at a fixed gain of
3. Maximum differential input voltage (VPIN4–VPIN3) is 1.1V.
Common-mode input voltage range is 0V to VIN – 3V.
Resistive-sensing methods are shown in Figure 2. In
Figure 2(A), a simple RC filter limits transient voltage spikes
at pin 4, caused by external output transistor-collector
capacitance. Transformer coupling (Figure 3) offers isola-
tion and better power efficiency, but cost and complexity
increase.
Inordertominimizethepropagationdelayfromtheinput
to the current amplifier to the output terminals, the current
ramp should be in the order of 1µsec in width (min). Typical
time delay values are in the 225nsec region at 25°C. The
delay time increases with device temperature so that at
50°C, the delay times may be increased by as much as
100nsec.
The outputs can be turned OFF quickly through the
SHUTDOWN input (pin 16). A signal greater than 360 mV
at pin 16 forces the shutdown comparator output HIGH.
The PWM latch is held set, disabling the outputs.
Q2 is also turned ON. If VREF/R1 is greater than 140µA,
positive feedback through the lock-up amplifier and Q1
keeps the inverting PWM comparator inverting input below
0.65V. Q3 remains ON even after the shutdown input
signal is removed. This is because the lock-up amplifier is
in latched mode driving Q3 ON. This state can be cleared
only through a power-up cycle. Outputs will be disabled
whenever the potential at pin 1 is below 0.65V.
The shutdown terminal gives a fast, direct way to dis-
able the PWM controller output transistors. System protec-
tion and remote shutdown applications are possible.
TELCOM SEMICONDUCTOR, INC.
4-105
TELCOM [ TELCOM SEMICONDUCTOR, INC ]
