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TC170CPE 参数 Datasheet PDF下载

TC170CPE图片预览
型号: TC170CPE
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS电流模式PWM控制器 [CMOS CURRENT MODE PWM CONTROLLER]
分类和应用: 开关光电二极管控制器
文件页数/大小: 8 页 / 106 K
品牌: TELCOM [ TELCOM SEMICONDUCTOR, INC ]
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CMOS CURRENT MODE  
PWM CONTROLLER  
TC170  
The input pulse to pin 16 should be at least 500 nsec  
wide and have an amplitude of at least 1V in order to get the  
minimum propagation delay from input to output. If these  
parameters are met, the delay should be less than  
600nsec at 25°C; however, the delay time will increase as  
the device temperature rises.  
Peak Current Limit Setup  
Resistors R1 and R2 at the current limit input (pin 1)  
set the TC170 peak current limit (Figure 1). The potential at  
pin 1 is easily calculated:  
R2  
V1 = VREF  
R1 + R2  
Soft Restart From Shutdown  
R1 should be selected first. The shutdown circuit fea-  
ture is not latched for (VREF – 0.35)/R1 < 50µA and is  
latched for currents greater than 125µA.  
The error amplifier output voltage is clamped from  
going above V1 through the limit buffer amplifier. Peak  
current is sensed by RS and amplified by the current  
amplifier which has a fixed gain of 3.15.  
IPCL, the peak current limit, is the current that causes  
the PWM comparator noninverting input to exceed V1, the  
potential at the inverting input. Once the comparator trip  
point is exceeded, both outputs are disabled.  
A soft restart can be programmed if nonlatched shut-  
down operation is used.  
A capacitor at pin 1 will cause a gradual increase in  
potential toward V1. When the voltage at pin 1 reaches  
0.75V, the PWM latch set input is removed and the circuit  
establishesaregulatedoutputvoltage. Thesoft-startopera-  
tion forces the PWM output drivers to initially operate with  
minimum duty cycle and low peak currents.  
Even if a soft start is not required, it is necessary to  
insert a capacitor between pin 1 and ground if the current IL  
is greater than 125µA. This capacitor will prevent "noise  
triggering" of the latch, yet minimize the soft-start effect.  
IPCL is easily calculated:  
V1 – 0.75V  
IPCL  
where:  
=
Soft-Start Power-Up  
3.15 (RS)  
During power-up, a capacitor at R1, R2 initiates a soft-  
start cycle. As the input voltage (pin 15) exceeds the  
undervoltage lockout potential (7.7V), Q4 is turned OFF,  
ending undervoltage lockout. Whenever the PWM com-  
parator inverting input is below 0.5V, both outputs are  
disabled.  
When the undervoltage lockout level is passed, the  
capacitor begins to charge. The PWM duty cycle increases  
until the operating output voltage is reached. Soft-start  
operation forces the PWM output drivers to initially operate  
with minimum duty cycle and low peak current.  
R2  
V1 = VREF  
R1 + R2  
VREF = Internal voltage reference = 5.1V  
3.15 = Gain of current-sense amplifier  
0.75V = Current limit offset  
Both driver outputs (pins 11 and 14) are OFF (LOW)  
when the peak current limit is exceeded. When the sensed  
current goes below IPCL, the circuit operates normally.  
Current-Sense Amplifier  
Output Shutdown  
The current-sense amplifier operates at a fixed gain of  
3.15. Maximum differential input voltage (VPIN4 – VPIN3) is  
1.1V. Common-mode input voltage range is 0V to VIN – 3V.  
Resistive-sensing methods are shown in Figure 2. In  
Figure 2(A), a simple RC filter limits transient voltage spikes  
at pin 4, caused by external output transistor-collector  
capacitance. Transformer coupling (Figure 3) offers isola-  
tion and better power efficiency, but cost and complexity  
increase.  
Inordertominimizethepropagationdelayfromtheinput  
to the current amplifier to the output terminals, the current  
ramp should be in the order of 1 µs in width (min). Typical  
time delay values are in the 300 to 400nsec region at 25°C.  
The delay time increases with device temperature so that at  
50°C, the delay times may be increased by as much as  
100nsec.  
The TC170 outputs can be turned OFF quickly through  
the shutdown input (pin 16). A signal greater than 350 mV  
at pin 16 forces the shutdown comparator output HIGH.  
The PWM latch is held set, disabling the outputs.  
Q2 is also turned ON. If VREF/R1 is greater than 125µA,  
positive feedback through the lock-up amplifier and Q1  
keeps the inverting PWM comparator inverting input below  
0.75V. Q3 remains ON even after the shutdown input  
signal is removed, because of the positive feedback. The  
state can be cleared only through a power-up cycle. Out-  
puts will be disabled whenever the potential at pin 1 is  
below 0.75V.  
The shutdown terminal gives a fast, direct way to dis-  
able the TC170 output transistors. System protection and  
remote shutdown applications are possible.  
4-122  
TELCOM SEMICONDUCTOR, INC.