HV583
Pad Description
Vpp
High voltage supply for outputs.
Vdd
Low voltage logic supply
D1A to D4A
Right data input/output. Input when Dir=H, Output when Dir=L.
Left data input/output. Input when Dir=L, Output when Dir=H.
Dir=L or open, DXB to DXA shift. Dir=H, DXA to DXB shift.
Clock input. Data shifted from low to high transition.
Resets latches.
D1B to D4B
Dir
Clk
RST
LE
Latch enable. Data latches during rising edge LE.
Output enable bar. HVout high impedance control.
Output low bar. HVout=low when this pin is low.
OH bar input.
OE
OL
OH
DGND
Digital logic ground.
PGND
HVout output ground.
HVout0 to HVout127
High voltage outputs.
Pad Location
HVOUT64
HVOUT63
HVOUT127
HVOUT0
VPP
VPP
PGND
PGND
5
SUPERTEX [ Supertex, Inc ]
