HV57708
Functional Block Diagram
D
D
1
D
2
D
D
3
D
D
4
O
O
O
O
4
D
3
2
1
I
V
LE
BL
POL
V
PP
I
I
I
DD
HV
HV
HV
1
5
9
•
OUT
OUT
OUT
DIR
SR1
•
•
61
2
6
10
•
SR2
•
•
HV
HV
62
OUT
CLK
3
7
OUT
11
•
SR3
•
•
HV
HV
HV
63
OUT
OUT
4
8
12
•
SR4
•
•
64
OUT
D
D
4
D
3
D
D
2
D
D
1
O
GND
O
O
O
1
D
2
3
4
I
I
I
I
Note: Each SR (shift register) provides 16 outputs. SR1 supplies every fourth output starting with 1; SR2 supplies every fourth output with 2, etc.
Function Table
Inputs
LE
Outputs
Function
Shift Reg
HV Outputs
Data Out
Data
CLK
BL
POL
DIR
All O/P High
All O/P Low
O/P Normal
O/P Inverted
X
X
X
X
L
X
X
X
X
↑
X
X
X
X
H
H
H
H
L
L
L
L
H
H
L
X
X
X
X
X
X
X
X
X
X
H
L
H
H
H
H
H
H
H
H
No inversion
Inversion
H
H
L
L
H
L
H
*
L
Data Falls
Through
(Latches
H
L
H
↑
H
↑
Transparent)
H
X
X
L
L
↑
X
X
H
L
Stored Data
Data Stored/
Latches Loaded
L
*
Inversion of
Stored Data
D
I/O1-4A
H
L
H
H
H
H
H
H
Qn→ Qn +1
Qn→ Qn +1
New H or L
DI/O1 – 4B
DI/O1 – 4B
↑
↑
DI/O1-4A
DI/O1-4B
DI/O1-4B
Previous
H or L
I/O Relation
L
H
H
H
H
L
L
Qn→ Qn -1
Qn→ Qn -1
Previous
H or L
DI/O1 – 4A
DI/O1 – 4A
↑
↑
H
New H or L
Note: * = dependent on previous stage’s state. See Pin configuration for D and D
pin designation for CW and CCW shift.
IN
OUT
12-94
SUPERTEX [ Supertex, Inc ]
