HV510
Functional Block Diagram
POL
VPP
BL
LE
DIOA
HVOUT
1
2
L/T
L/T
CLK
HVOUT
•
•
•
12-bit
Static Shift
Register
8 Additional
Outputs
12 Latches
DIR
•
•
•
HVOUT11
L/T
HVOUT12
L/T
L/T = Level Translator
DIOB
Function Table
Inputs
Outputs
Function
Shift Reg
HV Outputs
Data Out
Data
CLK
LE
BL
POL
DIR
1
2…12
1
2…12
H…H
L…L
*…*
*
All on
X
X
X
X
↑
X
X
↑
↑
↑
↑
X
X
L
L
L
L
H
L
X
X
X
X
X
X
X
X
L
*
*…*
H
L
*
*
All off
X
X
*
*
*…*
*
Invert mode
Load S/R
H
H
H
H
H
H
X
X
*…*
*
H or L
X
L
H
H
L
H or L *…*
*
*…*
*
↓
↓
H
H
X
X
*
*
*…*
*…*
*…*
*…*
*
*…*
*
*
Store data
in latches
X
*
*…*
L
H
H
X
X
L
H
L
H
*…*
*
Transparent
latch mode
H
*…*
*
DIOA
DIOB
Qn→ Qn-1
Qn→ Qn+1
—
DIOB
DIOA
I/O relation
H
—
Notes:
H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition, ↓ = high-to-low transition.
* = dependent on previous stage’s state before the last CLK or last LE high.
4
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