HV508
Truth Table
HVEN
POL
H
HVOUT1
HVIN
HVOUT2
GND
HVIN
H
H
L
L
GND
LVIN
H
GND
LVIN
L
L
GND
Timing Diagram
VIH
VIL
POL
50%
50%
VIN
or LVIN
80%
HVOUT1
GND
5%
t(ON)
t(OFF)
Figure 1
VIH
HVEN
50%
VIL
HVIN
80%
HVOUT1
LVIN
tEN
(ON)
Figure 2
Block Diagram
LV
IN
HV
Level
Translator
IN
Level
Translator
V
DD
HV
1
OUT
CMOS
Logic
HV
EN
Level
Translator
POL
Level
Translator
GND
HV
2
OUT
12/13/010
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com
3
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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