HV4937
Functional Block Diagram
VSS
Output Enable
Latch Enable
Data Input
HVOUT
1
Clock
HVOUT
2
•
•
•
64 bit
Static Shift
Register
64 Latches
DIR
60 Additional
Outputs
•
•
•
HVOUT63
HVOUT64
Data Out
Function Table
Inputs
Outputs
HVOUT
1 2 … 64 1 2 … 64
Function
Data
CLK
LE
OE
DIR
Shift Reg
Latch
DOUT
1 2 … 64
All off
X
H or L
H or L
H or L
X
X
X
L
L
L
X
H
L
*…*
*…*
*…*
H…H
H…H
H…H
H…H
*
*
*
*
*
*
*
Load S/R
↓
H or L…Qn → Qn+1
H or L…Qn → Qn-1
H or L…*
↓
L
L
*…*
Load Latch
↓
H
H
H
H
L
X
X
X
X
H or L…*
H or L
H
H
H
H or L…*
H or L…* L or H…*
Output Enable
Transparent Latch
Mode
H
↓
↓
H…*
H…*
L…*
L …*
H…*
L
L …*
Notes:
X = Don’t care
* = Dependent on previous stage’s state before the last CLK : High to low transition.
↓ = -5V to V transition
SS
H = V
DD
SS
L = V
12-32
SUPERTEX [ Supertex, Inc ]
