HV440
Block Diagram
VPP1
Current
Sense
and
Vpsen
High
Voltage
Level
Driver
VDD
Translator
Pgate
VPP2
Linear
Reg
PIN
NIN
EN
HVOUT
PGND
Logic
VDD
Mode
Linear
Reg
VNN2
Ngate
High
Voltage
Level
GND
Translator
Current
Sense
and
Vnsen
Driver
VNN1
Pin Description
VPP1
VPP2
Positive high voltage supply.
Positive gate voltage supply. Generated by an internal linear regulator. A 0.1µF capacitor should be connected between
VPP2 and VPP1
.
VNN1
VNN2
Negative high voltage supply.
Negative gate voltage supply. Generated by an internal linear regulator. A 0.1µF capacitor should be connected between
VNN2 and VNN1
.
VDD
Logic supply voltage.
GND
PGND
PIN
Low voltage ground.
High voltage power ground.
Logic control input. When mode is high, logic input high turns OFF output high voltage P-Channel.
Logic control input. When mode is high, logic input high turns ON output high voltage N-Channel.
Logic enable bar input. Logic low enables IC.
NIN
EN
Mode
Logic mode input. Logic low activates 200nsec deadband. When mode is low, NIN turns on and off the high voltage N- and
P-Channels. Pin is not used and should be connected to VDD or ground.
HVOUT
Vpsen
Vnsen
Pgate
High voltage output. Voltage swings from VPP1 to VNN1.
Pulse by pulse over current sensing for P-Channel MOSFET.
Pulse by pulse over current sensing for N-Channel MOSFET.
Gate drive for external P-channel MOSFET.
Ngate
Gate drive for external N-channel MOSFET.
3
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