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HV430WG-G 参数 Datasheet PDF下载

HV430WG-G图片预览
型号: HV430WG-G
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom Circuit, 1-Func, CMOS, PDSO20, 12.80 X 7.50 MM, 2.65 MM HEIGHT, 1.27 MM PITCH, GREEN, MS-013AC, SOW-20]
分类和应用: 高压
文件页数/大小: 8 页 / 120 K
品牌: SUPERTEX [ Supertex, Inc ]
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HV430  
Pin Description  
VPP1  
VPP2  
Positive high voltage supply.  
Positive gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should be  
connected between VPP2 and VPP1  
Negative high voltage supply.  
.
VNN1  
VNN2  
Negative gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should be  
connected between VNN2 and VNN1  
Logic supply voltage.  
.
VDD  
SGnd  
PGnd  
PIN  
Low voltage logic ground.  
High voltage power ground.  
Logic control input. When mode is high, logic input high turns ON the external high voltage P-channel MOSFET.  
Internally pulled low.  
NIN  
Logic control input. When mode is high, logic input high turns ON the external high voltage N-channel MOSFET.  
Internally pulled low.  
ENABLE  
MODE  
Logic enable input. Logic high enables IC. Internally pulled low.  
Logic mode input. 0=single-control; 1=dual-control. When MODE is high, NIN and PIN independently control NOUT  
and POUT, respectively. When MODE is low, NIN controls both outputs in a complementary manner.  
(See Truth Table)  
FAULT  
RESET  
Logic output. Fault is at logic low when either current limit sense pin, VPsen or VNsen, is activated. Remains  
active until overcurrent condition clears or ENABLE=0 or RESET=0.  
Power-on reset. A capacitor connected between this pin and ground determines the delay time between application  
of VDD and when the device outputs are enabled. Low leakage tantalum recommended.  
DEADBAND A resistor between this pin and ground sets the ‘break-before-make’ time between output transitions. Applicable  
only in single-control mode. For minimum deadtime, a 5.6kresistor to ground should be used. For dual-input  
mode, tie to Vdd.  
VPgate  
VNgate  
VPsen  
VNsen  
Gate drive for external P-channel MOSFET.  
Gate drive for external N-channel MOSFET.  
Pulse by pulse over current sensing for P-Channel MOSFET.  
Pulse by pulse over current sensing for N-Channel MOSFET.  
Pin Configuration  
VDD  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VPP2  
2
Fault  
VPP1  
3
Mode  
VPSEN  
VPGATE  
N/C  
4
PIN  
5
NIN  
6
Enable  
Reset  
Deadband  
SGND  
PGND  
N/C  
7
VNGATE  
VNSEN  
VNN1  
8
9
10  
VNN2  
top view  
SOW 20  
12/13/010  
1235 Bordeaux Drive, Sunnyvale, CA 94089  
TEL: (408) 744-0100 • FAX: (408) 222-4895  
www.supertex.com  
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.