HV300DB1
HV300DB1 Schematic
V
V
DD
EE
+
+
R1
487KΩ
V
DD
UV
PWRGD
PG
J1
R2
9.09KΩ
48V
Output
HV300LG
OV
48V
Input
C
load
100µF
V
Ramp
Sense Gate
EE
R3
9.09KΩ
Cramp
10nF
-
-
V
M1
IRFR120N
Drain
EE
Rsense
0.05Ω
Bill of Materials for HV300DB1 Demo Board
Designator
Description
Value/Rating Package
Part Number
Manufacturer
--
J1
Wire Jumper
--
--
--
R1
R2
R3
Thick film chip resistor
Thick film chip resistor
Thick film chip resistor
Thick film chip resistor
Ceramic chip capacitor, X7R
Electrolytic capacitor
N-Channel MOSFET
Hot Swap IC
487K
9.09K
9.09K
0.05
1%
1%
1%
1%
0805
0805
0805
1206
0805
--
ERJ6ENF487K
ERJ6ENF9.09K
ERJ6ENF9.09K
WSL1206-.05
Panasonic
Panasonic
Panasonic
Dale
R
SENSE
RAMP
C
10nF, 50V
100µF, 160V
100V, 0.21
90V
ECJ-2VB1H103K Panasonic
C
LOAD
M1
ECA-2CHG101
IRFR120N
Panasonic
Dpak
SO-8
International Rectifier
Supertex Inc.
HV300
HV300LG
HV300 Typical Waveforms
Notes:
1) Some versions of the HV300DB1 may include a 10nF
capacitor from IC pins 5 to 6 (the MOSFET gate to source).
This capacitor is used to eliminate ringing at the end of the
inrush period.
Drain
50V/div
2) Current can be measured with a current probe on the Vdd
line. The current drawn by the load can be measured by
replacing J1 with a small resistor and measuring the voltage
drop. Alternatively, a current probe can be used by replacing
J1 with a wire loop.
VIN
50V/div
Gate
5.00V/div
3) PG is an open drain output and will have no effect if probed
without a pullup.
4. The dual plateau characteristic of the gate response is an
intended result of Supertex’s closed loop hot swap solution.
The steep voltage jump of the gate occurs after the MOSFET
is fully on and indicates the point at which the IC goes into
sleep mode (PG high).
Iinrush
500mA/div
5.00ms/div
05/16/01
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
PB
SUPERTEX [ Supertex, Inc ]
