HV2701
Logic Function Table
LATCH
ENABLE
INPUT DATA
CLOCK
OUTPUT SWITCH
Notes:
1.
Th 16 switches operate independently.
Serial data is clocked in on the L to H transition of the CLK.
All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch.
2.
3.
4.
5.
6.
D
OUT is high when data in the register 15 is high.
Shift registers clocking has no effect on the switch states if LE is high.
The CL clear input overrides all other inputs.
Logic Timing Waveforms
D
D
D
N + 1
N – 1
N
DATA
IN
50%
50%
50%
50%
t
LE
WLE
t
SD
50%
50%
CLOCK
t
t
h
SU
t
DO
DATA
OUT
50%
t
t
OFF
ON
OFF
ON
V
OUT
(TYP)
90%
10%
50%
50%
CLR
t
WCL
NR102405
6
SUPERTEX [ Supertex, Inc ]
