HV230/HV232
Truth Table
D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
OFF
ON
H
L
OFF
ON
H
L
OFF
ON
H
L
OFF
ON
H
L
OFF
ON
H
L
OFF
ON
H
L
OFF
ON
H
L
H
X
X
OFF
ON
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HOLD PREVIOUS STATE
OFF OFF OFF OFF OFF OFF OFF OFF
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is
low the shift register data flows through the latch.
4. D
is high when data in shift register 7 is high.
OUT
5. Shift register clocking has no effect on the switch states if LE is H.
6. The clear input overrides all other inputs.
Logic Timing Waveforms
D
DN
D N - 1
N + 1
DATA
IN
50%
50%
LE
50%
50%
t
WLE
t
SD
CLOCK
50%
50%
t
t
h
SU
t
DD
DATA
OUT
50%
t
t
OFF
ON
VOUT OFF
(TYP)
90%
10%
ON
50%
50%
CLR
tWCL
5
SUPERTEX [ Supertex, Inc ]
