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HV2221 参数 Datasheet PDF下载

HV2221图片预览
型号: HV2221
PDF下载: 下载PDF文件 查看货源
内容描述: 低电荷注入, 8通道,单极性,负高压,模拟开关 [Low Charge Injection, 8-Channel, Unipolar, Negative High Voltage, Analog Switch]
分类和应用: 开关高压
文件页数/大小: 8 页 / 705 K
品牌: SUPERTEX [ Supertex, Inc ]
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HV2221  
Pin Configuration  
Ordering Information  
48-Lead LQFP  
Device  
7x7mm body,  
1.6mm height (max), 0.50mm pitch  
HV2221  
HV2221FG-G  
-G indicates package is RoHS compliant (‘Green’)  
48  
1
48-Lead LQFP (FG)  
(top view)  
Absolute Maximum Ratings  
Parameter  
Product Marking  
Value  
-0.5V to +7.0V  
260V  
Top Marking  
VDD logic supply  
YYWW  
YY = Year Sealed  
WW = Week Sealed  
L = Lot Number  
HV2221FG  
VPP-VNN differential supply  
VPP positive supply  
LLLLLLLLL  
-0.5V to VNN+260V  
+0.5V to -250V  
-0.5V to VDD +0.3V  
VNN to VPP  
C = Country of Origin*  
A = Assembler ID*  
Bottom Marking  
VNN negative supply  
CCCCCCCC  
AAA  
= “Green” Packaging  
Logic input voltage  
*May be part of top marking  
Analog signal range  
48-Lead LQFP (FG)  
Peak analog signal current/channel  
Storage temperature  
Power dissipation  
4.5A  
-65°C to 150°C  
1.0W  
Absolute Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation under these conditions is not implied. Continuous operation of the device  
at the absolute rating level may affect device reliability. All voltages are referenced to device  
ground.  
Operating Conditions  
Sym  
VDD  
Parameter  
Value  
3.0V to 5.5V  
240V  
Logic power supply voltage  
Supply voltage differential  
Positive driver supply  
VPP - VNN  
VPP  
+15V to +50V  
VNN  
Negative high voltage supply  
High level input voltage  
Low-level input voltage  
Analog signal voltage peak-to-peak  
Operating free air temperature  
-100V to -225V  
0.9VDD to VDD  
VIH  
VIL  
0V to 0.1VDD  
VSIG  
TA  
VNN +10V to VPP -10V  
0OC to 70OC  
Notes:  
1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.  
2. SIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition.  
V
3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec.  
2