HV220/HV20220/HV20320
Truth Table
D0
L
D1
D2
D3
D4
D5
D6
D7
LE
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
CLR SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
Off
On
H
L
Off
On
H
L
Off
On
H
L
Off
On
H
L
Off
On
H
L
Off
On
H
L
Off
On
H
L
H
X
X
Off
On
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Hold Previous State
All Switches Off
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition of the CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch.
4. DOUT is high when data in the shift register 7 is high.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The CLR clear input overrides all other inputs.
Logic Timing Waveforms
D N + 1
D
DN - 1
N
DATA
IN
50%
50%
50%
LE
50%
t
WLE
t
SD
CLOCK
50%
50%
t
t
h
SU
t
DD
DATA
OUT
50%
t
t
OFF
ON
VOUT OFF
(TYP)
90%
10%
ON
50%
50%
CLR
tWCL
5
SUPERTEX [ Supertex, Inc ]
