HV214
Truth Table
Data in 8-Bit Shift Register
Output Switch State
SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
LE
CL
D0 D1 D2 D3 D4 D5 D6 D7
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
OFF
ON
OFF
ON
H
L
H
OFF
ON
L
H
OFF
ON
L
H
OFF
ON
L
H
OFF
ON
L
H
OFF
ON
L
H
X
X
OFF
ON
Hold Previous State
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OFF OFF OFF OFF OFF OFF OFF OFF
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L→H transition CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch.
4. DOUT is high when switch 7 is on.
5. Shift register clocking has no effect on the switch states if LE is H.
6. The clear input overrides all other inputs.
Logic Timing Waveforms
D
D
D
N - 1
N + 1
N
DATA
IN
50%
50%
50%
50%
t
LE
WLE
t
SD
50%
50%
CLOCK
t
t
h
SU
t
DO
DATA
OUT
50%
t
t
OFF
ON
OFF
V
OUT
(TYP)
90%
10%
ON
50%
50%
CLR
t
WCL
5
SUPERTEX [ Supertex, Inc ]
