SUMMIT
MICROELECTRONICS, Inc.
SMP9210 SMP9211 SMP9212
Table 1. Command Structure.
MSB
LSB
0
Command
7
1
1
6
0
0
5
0
1
4
1
0
3
2
1
Function
Write 10-bit value to DAC1
Write 10-bit value to DAC2
dc
dc
dc
dc
D9
D9
D8
D8
Write DAC1
Write DAC2
Write the same 10-bit value to DAC1
and DAC2
1
0
1
1
dc
dc
D9
D8
Write Both DACS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
1
0
1
1
ZeroDAC1
ZeroDAC2
ZeroBOTH
3FDAC1
Set DAC1 to Zero Scale (VREFL
Set DAC2 to Zero Scale (VREFL
)
)
1
1
Set DAC1 & DAC2 to Zero Scale (VREFL)
1
1
Set DAC1 to Full Scale (VREFL
Set DAC2 to Full Scale (VREFL
)
)
1
1
3FDAC2
1
1
3FBOTH
Set DAC1 & DAC2 to Full Scale (VREFL
Recall E2 to DAC1
Recall E2 to DAC2
)
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
RecallDAC1
RecallDAC2
RecallBoth
PDDAC1
Recall E2 to Both DACs
Power Down DAC1 (VOUT to GND)
Power Down DAC2 (VOUT to GND)
PDDAC2
PDBOTH
Power Down Both DACs (VOUT to GND)
*dc = don't care
type/address byte followed by the command byte.
They are will be enforced with or without a stop being
issued and the new register value is never stored in
the nonvolatile register.
set to zero. The SMP9210 will respond with an
acknowledge and the master will then issue the
command and follow-on data. In the example below
the write is to DAC1, where the command = 1001[b];
the dc bits are don't care, D9 and D8 are the MSBs of
the DAC value being written. The SMP9210 will then
respond with an acknowledge followed by the master
writing the last eight bits. In the first example shown,
no stop is generated after the SMP9210
acknowledge; therefore, the write is only to the
register. In the second example the SMP9210
acknowledge is followed by a stop; therefore, the
data is written to both the DAC register and to the
nonvolatile register.
Writing a value to a DAC can either be a write to the
DAC register only or a combined write to both the
DAC Register and its nonvolatile register. They are
identical with the one exception being the register
write does not entail issuing a stop condition;
whereas, the nonvolatile write operation is concluded
with a stop.
The sequence is to issue a start, followed by the
device type and bus address, with the read/write bit
Writing to DACs Data Sequence (Volatile Write)
S
A
C
K
A
C
K
t
a
r
A
2
A
1
A
0
d
c
d
c
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
0
1
0
1
0
1
0
0
1
1
0
t
Device Type and Bus Address
W
Command
Writing to DACs Data Sequence (Nonvolatile Write)
S
t
a
r
S
t
o
p
A
2
A
1
A
0
A
C
K
d
c
d
c
D
9
D
8
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
0
1
0
1
0
1
0
1
0
1
t
Command Sequence (example command shown 3FDAC1)
S
t
a
r
A
C
K
A
C
K
A
2
A
1
A
0
0
1
0
1
0
1
1
1
1
0
t
Device Type and Bus Address
W
Command
Advance Information
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