SMM205
Preliminary Information
PIN DESCRIPTIONS
Pin
Pin
Pin Name
Pin Description
Number
Type
DATA SDA
I2C Bi-directional data line.
I2C clock input.
28
1
CLK
SCL
A2
I
I
I
2
The address pins are biased either to VDD_CAP or GND. When
communicating with the SMM205 over the 2-wire bus these pins provide a
mechanism for assigning a unique bus address.
A1
4
A0
6
Write Protect active low input. When asserted writes to the configuration
registers and general purpose EE are not allowed.
I
WP#
8
CAP
CAP
External capacitor input used to filter the VM inputs.
10
FILT_CAP
External capacitor input used for Active Control and margining.
15, 18
TRIM_CAPx
Output voltage used to control and/or margin converter voltages. Connect
to the converter trim input.
O
I
16, 20
14, 17
TRIMx
VMx
Voltage monitor input. Connect to the DC/DC converter positive sense line
or its +Vout pin.
Voltage reference input used for DC output control and margining.
VREF_CNTL can be programmed to output the internal 1.25V reference
voltage. Pin should be left open if using VREF internal.
I
9
21
7
VREF_CNTL
VDD
PWR
GND
Power supply of the part.
Ground of the part. The SMM205 ground pin should be connected to the
ground of the device under control or to a star point ground. PCB layout
should take into consideration ground drops.
GND
12V power supply input internally regulated to either 3.6V or 5.5V. When
using the 3.6V internal regulator option the voltage input can be as low as
8V. It can be as high as 15V using the 5.5V internal regulator.
PWR
I
22
3
12VIN
Programmable active high/low input. The START input is used solely for
enabling Active Control and/or margining.
START
Programmable active high/low open drain output indicates that VM is at its
set point. When programmed as an active high output READY can also be
used as an input. When pulled low it will latch the state of the comparator
inputs.
I/O
5
READY
CAP
I
External capacitor input used to filter the internal supply rail.
23
19
VDD_CAP
COMP1
COMP1 and COMP2 are high impedance inputs, each connected internally
to a comparator and compared against the VREF_CNTL input. Each
comparator can be independently programmed to monitor for UV or OV.
The monitor level is set externally with a resistive voltage divider.
I
12
COMP2
When either of the COMP1 or COMP2 inputs are in fault the open-drain
FAULT# output will be pulled low. A configuration option exists to disable
the FAULT# output while the device is margining.
O
11
FAULT#
NC
NC
No Connect. Leave floating; do not connect anything to the NC pins.
13, 24-27
Summit Microelectronics, Inc
2069 1.4 6/23/03
4
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
