SMH4803
SMH4803 Pin Descripiton
When CBMode is tied to 5V the circuit breaker will be
placed in the self-restart or cycling mode. The state of
CBReset# input will control the operation of the restart. If
CBReset# is tied to 5V the Vgate output will automatically
PIN NAME (Pin #)
Drain Sense (1)
The Drain Sense input monitors the voltage at the drain of restart after tCYC has elapsed. If the fault condition still
the external power MOSFET switch with respect to VSS exists, the circuit breaker will trip once again. The cycling
.
When the MOSFET is turned on, the Drain Sense input will continue until the fault clears or the circuit board is
will be driven low and will be used as one of the enable replaced. Alternatively the CBReset# input can be ac-
conditions for the PG outputs. This will prevent any tively driven to VSS. If a fault occurs the Vgate and PG
premature activation of the PG outputs.
outputs will not be turned on again for tCYC after the
CBReset# input is driven high.
Vgate (2)
CBSense (9)
The Vgate output activates an external power MOSFET
switch. It is a constant current source (100µA typical) The circuit breaker sense input is used to detect
allowing easy programming of the MOSFET turn on slew overcurrent conditions in the load connected to the power
rate.
MOSFET. A low value sense resistor (RS) is tied in series
with the MOSFET switch; one end tied to VSS and the
othertotheswitchandtheCBSenseinput. Avoltagedrop
of greater than 50mV (for greater than tCBD) across the
resistor will result in the circuit breaker tripping. A pro-
grammable“quick-trip”sensepointisalsoavailable. Ifthe
CBSenseinputtransitionsabovethethreshold, thecircuit
breaker will immediately trip.
EN/TS (3)
The Enable/Temperature Sense input is the master en-
able input. When EN/TS is LOW, Vgate, and the PG
outputs are off. As the name suggests, the EN/TS input
may be used as a master enable by a host system or
alternatively for circuit over-temperature protection using
an external thermistor.
VSS (10)
PD1# and PD2# (4 & 5)
The pin detect pins are active LOW inputs that are use to
prevent any power sequence before the add-in card is
VSS is connected to the negative side of the supply.
UV and OV (11 & 12)
properly seated. Both inputs must be at VSS before either The under-voltage (11) and over-voltage (12) input pins
Vgate or the PG outputs can be enabled.
monitor the supply voltage for the SMH4803 and the
downstream circuits. Both inputs have a 2.5V threshold
on their respective comparators. If UV is less than 2.5V or
if OV is greater than 2.5V, Vgate will be disabled.
Inapplicationswheremulti-lengthconnectorpinsareuse,
the PD inputs should be tied to the short pins. On the
mating connector side the pins opposite should be tied
directly to VSS. Alternatively, either one or both of the PD 5.0V (13)
inputs can be tied to card injector handle switches, insur-
ing no power sequencing will occur until the card is
properly seated.
5.0Visaprecision5voltoutputreferencevoltagethamay
be use to expand the logic-input funtions on the
SMH4803. The reference output is with respect to VSS
.
CBFault# (6)
2.5V (14)
CBFault#isanopendrainactivelowoutput, indicatingthe
circuit breaker status. When an over current condition is
detected CBFault# is driven low.
2.5V is a precision 2.5 volt output reference voltage tha
may be use to expand the logic-input funtions on the
SMH4803. The reference output is with respect to VSS
.
CBReset# (7)
ENPGB (15)
CBReset# is the circuit breaker reset input. It can be
activelycontrolledtoresetafaultconditionoritcanbetied
highorlowtoalloweithertimedrestarts(dutycyclemode)
or“latch-off”theVgateoutput. RefertotheCircuitBreaker
Operation and the associated timing diagrams for de-
tailed characteristics.
The ENPGB input may be used to independently switch
off the PG3# output. When ENPGB is pulled low, the
PG3# output is immediately placed in a high impedance
state. If PG2# is active and ENPGB is driven high, then
the PG3# output will immediately be driven low.
CBMode (8)
The CBMode input selects one of two circuit breaker
operational modes. When tied to VSS all fault conditions
must be cleared by toggling the CBReset# input low then
high.
2041 8.4 6/15/00
SUMMIT MICROELECTRONICS
8
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
