SMH4042A
V
V
&
TRIP
CC
HST_3V_MON
V
RVALID
LOCAL_PCI_RST#
RESET
t
HSE
BD_SEL1# &
BD_SEL2#
V
OHVG
VGATE3 &
VGATE5
t
SLEW
DRVREN#
CARD_3V_MON &
CARD_5V_MON
V
TRIP
t
PURST
HEALTHY#
SGNL_VLD#
2070 Fig01
Figure 1. Card Insertion Timing Diagram
Symbol
Description
Min.
Typ.
1
Max.
5
Units
µs
t
V
to Power Down Delay, Host Voltage Input
to Reset Output Delay, Card Voltage Input
TRIP
VTPD
TRIP
t
VTR
V
1
5
µs
t
PCI_RST# to LOCAL_PCI_RST#
Local Reset Output Valid
0.1
1
µs
PRLPR
V
1
V
RVALID
t
Slew Rate
250
200
200
40
V/s
ms
ms
ns
SLEW
t
HSE
BD_SEL# to Power On Delay, BD_SEL Noise Filter
Reset Timeout
100
100
150
150
t
PURST
t
Glitch Reject Pulse Width
GLITCH
t
Over-Current to Fault#
1
1
µs
OCF
t
Over-Current to VGATE Off
Circuit Breaker Time Constant, Power up
Circuit Breaker Time Constant, Operating
µs
OCVG
4
µs
t
CBTC
16
µs
2037 Table01 2.0
Table 1. Card Insertion Timing
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
7
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
