W144
Data Byte 6 (continued)
2
1
0
–
–
–
–
–
–
(Reserved)
(Reserved)
(Reserved)
–
–
–
–
–
–
0
0
0
Data Byte 7
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes[2]
Input Conditions
Output Frequency
Data Byte 0, Bit 3 = 1
Bit 2
SEL_3
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
CPU, SDRAM Clocks
PCI Clocks
(MHz)
(MHz)
133.6
124
150
140
105
110
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
33.4 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.7 (CPU/3)
39.3 (CPU/3)
40 (CPU/3)
115
120
100.2
133
112
33.4 (CPU/3)
44.3 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
103
66.8
83.3
75
124
Table 7. Select Function for Data Byte 0, Bits 0:1
Input Conditions
Data Byte 0
Output Conditions
CPU_F,
PCI_F,
PCI1:5
REF0:1,
IOAPIC
Function
Bit 1
Bit 0
CPU1
Note 1
0.5ꢀ
Hi-Z
48MHZ
24MHZ
24 MHz
24 MHz
Hi-Z
Normal Operation
Spread Spectrum
0
1
1
0
0
1
Note 1
0.5ꢀ
Hi-Z
14.318 MHz
14.318 MHz
Hi-Z
48 MHz
48 MHz
Hi-Z
Three-state
Note:
2. CPU and PCI frequency selections are listed in Table 1 and Table 6.
Rev 1.0,November 21, 2006
Page 8 of 13
SPECTRALINEAR [ SPECTRALINEAR INC ]
