W137
Upon W137 power-up, the first 2 ms of operation are used for
input logic selection. During this period the output buffers are
tri-stated, allowing the output strapping resistor on each l/O pin
to pull the pin and its associated capacitive clock load to either
a logic HIGH or logic LOW state. At the end of the 2-ms period,
the established logic 0 or 1 condition of each l/O pin is then
latched. Next, the output buffers are enabled, which converts
both l/O pins into operating clock outputs. The 2-ms timer is
started when VDD reaches 2.0V. The input latches can only be
reset by turning VDD off and then back on again.
Overview
The W137 was developed to meet the Intel® Mobile Clock
specification for the BX chipset, including Super I/O and USB
support. The W40S11-02 is the Intel-defined companion part
used for driving 2 SDRAM DIMM modules. Please see that
data sheet for additional information.
Cypress’s proprietary spread spectrum frequency synthesis
technique is a feature of the CPU and PCI outputs. When
enabled, this feature reduces the peak EMI measurements of
not only the output signals and their harmonics, but also of any
other clock signals that are properly synchronized to them.
The –0.±% modulation profile matches that defined as
acceptable in Intel’s clock specification.
It should be noted that the strapping resistors have no signif-
icant effect on clock output signal integrity. The drive
impedance of the clock output is <40: (nominal) which is
minimally affected by the 10-k: strap to ground or VDD. As with
the series termination resistor, the output strapping resistor
should be placed as close to the l/O pin as possible in order to
keep the interconnecting trace short. The trace from the
resistor to ground or VDD should be kept less than two inches
in length to prevent system noise coupling during input logic
sampling.
Functional Description
I/O Pin Operation
Pins 14, 26, and 27 are dual-purpose l/O pins. Upon power-up
these pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of each pin is latched and the pins then become
clock outputs. This feature reduces device pin count by
combining clock outputs with input select pins.
When the clock outputs are enabled following the 2-ms input
period, target (normal) output frequency is delivered assuming
that VDD has stabilized. If VDD has not yet reached full value,
output frequency initially may be below target but will increase
to target once VDD voltage has stabilized. In either case, a
short output clock cycle may be produced from the CPU clock
outputs when the outputs are enabled.
An external 10-k: “strapping” resistor is connected between
each l/O pin and ground or VDD. Connection to ground sets a
latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connection.
Figure 1. Input Logic Selection Through Resistor Load Option
Figure 2. Input Logic Selection Through Jumper Option
Rev 1.0,November 24, 2006
Page 3 of 8
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