W137
PCI Clock Outputs, PCI1:5 and PCI_F (Lump Capacitance Test Load = 30 pF)
CPU = 66.6/100 MHz
Parameter
tP
Description
Period
Test Condition/Comments
Measured on rising edge at 1.±V
Min.
Typ.
Max.
Unit
30
ns
tH
tL
tR
tF
tD
tJC
tSK
tO
fST
High Time
Low Time
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
12.0
12.0
1
ns
ns
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate Measured from 2.4V to 0.4V
4
4
V/ns
V/ns
%
1
Duty Cycle
Measured on rising and falling edge at 1.±V
4±
±±
2±0
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.±V. Maximum difference
of cycle time between two adjacent cycles.
ps
Output Skew
Measured on rising edge at 1.±V
±00
4.0
ps
ns
CPU to PCI Clock Offset Covers all CPU/PCI outputs. Measured on rising edge
at 1.±V. CPU leads PCI output.
1.±
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
3
ms
from Power-up (cold
start)
Zo
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
20
:
REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Determined by crystal oscillator frequency
Measured from 0.4V to 2.4V
Min.
14.318
0.±
Max.
Typ.
Unit
MHz
V/ns
V/ns
%
f
tR
2
2
tF
Measured from 2.4V to 0.4V
0.±
tD
Measured on rising and falling edge at 1.±V
4±
±±
3
fST
Frequency Stabilization from Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
ms
Power-up (cold start)
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
2±
:
48 MHz and 24 MHz Clock Outputs (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max. Unit
f
Frequency, Actual
Determined by PLL divider ratio (see n/m below)
48.008
24.004
MHz
fD
Deviation from 48 MHz
PLL Ratio
(48.008 – 48)/48
+167
ppm
m/n
tR
(14.31818 MHz x ±7/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
±7/17, ±7/34
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.±
0.±
4±
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.±V
±±
3
fST
FrequencyStabilizationfrom Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
ms
Power-up (cold start)
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
2±
:
Rev 1.0,November 24, 2006
Page 7 of 8
SPECTRALINEAR [ SPECTRALINEAR INC ]
