SL23EP09
General Description
Select Input Control
The SL23EP09 is a low skew, low jitter Zero Delay Buffer
with very low operating current.
The SL23EP09 provides two (2) input select control pins
called S1 and S2. This feature enables users to selects
various states of output clock banks-A and bank-B, output
source and PLL shutdown features as shown in the Table 2.
The product includes an on-chip high performance PLL that
locks into the input reference clock and produces nine (9)
output clock drivers tracking the input reference clock for
systems requiring clock distribution.
The S1 (Pin-9) and S2 (Pin-8) inputs include 250 kȍ weak
pull-up resistors to VDD.
in addition to CLKOUT that is used for internal PLL
feedback, there are two (2) banks with four (4) outputs in
each bank, bringing the number of total available output
clocks to nine (9).
PLL Bypass Mode
If the S2 and S1 pins are logic High(1) and Low(0)
respectively, the on-chip PLL is shutdown and bypassed,
and all the nine output clocks bank A, bank B and CLKOUT
clocks are driven directly from the reference input clock. In
this operation mode SL23EP09 works like a non-ZDB fanout
buffer.
Input and output Frequency Range
The input and output frequency range is the same. But, it
depends on VDD and drive levels as given in the below
Table 1.
VDD(V)
3.3
Drive
HIGH
STD
Min(MHz)
Max(MHz)
220
High and Low-Drive Product Options
10
10
10
10
The SL23EP09 is offered with High-Drive “-1H” and
Standard-Drive “-1” options. These drive options enable the
users to control load levels, frequency range and EMI
control. Refer to the AC electrical tables for the details.
3.3
167
2.5
HIGH
STD
200
2.5
133
Skew and Zero Delay
Table 1. Input/Output Frequency Range
All outputs should drive the similar load to achieve output-to-
output skew and input-to-output specifications given in the
AC electrical tables. However, Zero delay between input
and outputs can be adjusted by changing the loading of
CLKOUT relative to the banks A and B clocks since
CLKOUT is the feedback to the PLL.
If the input clock frequency is DC (GND to VDD), this is
detected by an input frequency detection circuitry and all
nine (9) clock outputs are forced to Hi-Z. The PLL is
shutdown to save power. In this shutdown state, the product
draws less than 12 ȝA supply current.
Power Supply Range (VDD)
SpreadThru™ Feature
If a Spread Spectrum Clock (SSC) were to be used as an
input clock, the SL23EP09 is designed to pass the
modulated Spread Spectrum Clock (SSC) signal from its
reference input to the output clocks. The same spread
characteristics at the input are passed through the PLL and
drivers without any degradation in spread percent (%),
spread profile and modulation frequency
The SL23EP09 is designed to operate in a wide power
supply range from 2.3V (Min) to 3.6V (Max). An internal on-
chip voltage regulator is used to supply PLL constant power
supply of 1.8V, leading to a consistent and stable PLL
electrical performance in terms of skew, jitter and power
dissipation. Contact SLI for 1.8V power supply version ZDB
called SL23EPL09.
Rev 1.1, February 2, 2007
Page 3 of 13
SPECTRALINEAR [ SPECTRALINEAR INC ]
