SL23EP08
Figure 1. CLKIN Input to CLKA and CLKB Delay
PLL Shutdown
and Bypass
S2
S1
Clock A1-A4
Clock B1-B4
Output Source
0
0
1
1
0
1
0
1
Tri-state
Driven
Driven
Driven
Tri-state
Tri-state
Driven
PLL
PLL
Yes
No
Reference(CLKIN)
PLL
Yes
No
Driven
Table 2. Select Input Decoding
Feedback From Bank-A Frequency
Device
Bank-B Frequency
Reference
SL23EP08-1 and 1H
SL23EP08-2 and -2H
SL23EP08-2 and -2H
Bank-A or Bank-B
Bank-A
Reference
Reference
[1]
[1]
Reference/2
Bank-B
Bank-A
2x Reference
2xReference
4xReference
2x Reference
Reference/2
Reference
[1]
[2]
SL23EP08-3
Reference
[1]
Bank-B
2xReference
2x Reference
Reference/2
SL23EP08-3
SL23EP08-4
Bank-A or Bank-B
Bank-A or Bank-B
SL23EP08-5H
Table 3. Available SL23EP08 Configurations
Notes:
1. Outputs are inverted on SL23EP08-2, -2H and -3 in PLL bypass mode when S2=1 and S1=0. Use SL23EP08-1 if
non-inverting outputs are required.
2. Output phase is random (0° or 180° with respect to input clock). Use SL23EP08-2 if phase integrity is required.
Rev 1.4, May 28, 2007
Page 4 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
